This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13-?m 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 dB and consumes 0.826 mW, resulting in a figure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only 195 × 265 ?m2.

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A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.

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A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

A 500-MS/s 5-bit ADC for UWB applications has been fabricated in a 65-nm CMOS technology using no analog-specific processing options. The time-interleaved successive approximation register (SAR) architecture has been chosen due to its simplicity versus flash and its amenability to scaled technologies versus pipelined, which relies on operational amplifiers. Six time-interleaved channels are used, sharing a single clock operating at the composite sampling rate. Each channel has a split capacitor array that reduces switching energy, increases speed, and has similar INL and decreased DNL, as compared to a conventional binary-weighted array. A variable delay line adjusts the instant of latch strobing to reduce preamplifier currents. The ADC achieves Nyquist performance, with an SNDR of 27.8 and 26.1 dB for 3.3and 239 MHz inputs, respectively. The total active area is 0.9mm2, and the ADC consumes 6 mW from a 1.2-V supply

500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC

An asynchronous analog-to-digital converter (ADC) based on successive approximation is used to provide a high-speed (600-MS/s) and medium-resolution (6-bit) conversion. A high input bandwidth (>4 GHz) was achieved which allows its use in RF subsampling applications. By using asynchronous processing techniques, it avoids clocks at higher than the sample rate and speeds up a nonbinary successive approximation algorithm utilizing a series nonbinary capacitive ladder with digital radix calibration. The sample rate of 600 MS/s was achieved by time-interleaving two single ADCs, which were fabricated in a 0.13-mum standard digital CMOS process. The ADC achieves a peak SNDR of 34 dB, while only consuming an active area of 0.12mm2 and having power consumption of 5.3 mW

A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13- $\mu{\hbox{m}}$ CMOS

An 8-channel scalable EEG acquisition SoC is presented to continuously detect and record patient-specific seizure onset activities from scalp EEG. The SoC integrates 8 high-dynamic range Analog Front-End (AFE) channels, a machine-learning seizure classification processor and a 64 KB SRAM. The classification processor exploits the Distributed Quad-LUT filter architecture to minimize the area while also minimizing the overhead in power × delay . The AFE employs a Chopper-Stabilized Capacitive Coupled Instrumentation Amplifier to show NEF of 5.1 and noise RTI of 0.91 μVrms for 0.5-100 Hz bandwidth. The classification processor adopts a support-vector machine as a classifier, with a GBW controller that gives real-time gain and bandwidth feedback to AFE to maintain accuracy. The SoC is verified with the Children's Hospital Boston-MIT EEG database as well as with rapid eye blink pattern detection test. The SoC is implemented in 0.18 μm 1P6M CMOS process occupying 25 mm2, and it shows an accuracy of 84.4% in eye blink classification test, at 2.03 μJ/classification energy efficiency. The 64 KB on chip memory can store up to 120 seconds of raw EEG data.

An 8-Channel Scalable EEG Acquisition SoC With Patient-Specific Seizure Classification and Recording Processor

An asynchronous analog-to-digital converter (ADC) based on successive approximation is used to provide a high-speed (600-MS/s) and medium-resolution (6-bit) conversion. A high input bandwidth ( 4 GHz) was achieved which allows its use in RF subsampling applications. By using asynchronous pro- cessing techniques, it avoids clocks at higher than the sample rate and speeds up a nonbinary successive approximation algorithm utilizing a series nonbinary capacitive ladder with digital radix calibration. The sample rate of 600 MS/s was achieved by time-in- terleaving two single ADCs, which were fabricated in a 0.13- m standard digital CMOS process. The ADC achieves a peak SNDR of 34 dB, while only consuming an active area of 0.12 mm and having power consumption of 5.3 mW. Index Terms—Analog-to-digital conversion, analog integrated circuits, asynchronous logic circuits, calibration, capacitive ladder, comparators, high-speed integrated circuits, impulse radio, non- binary successive approximation, ultra-wideband (UWB).

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A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS

To meet the huge computing demands of data-intensive applications, resource constrained IoT devices have to address the data migration issue, i.e., memory wall, in the conventional Von Neumann architecture to achieve the desired energy efficiency. Recently, Computing-in-Memory (CiM) has been considered as a promising alternative to overcome memory wall and extensively investigated for its deployment in IoT devices using SRAM, DRAM and Non-Volatile Memory (NVM). Among various devices, FeFET (Ferroelectric FET) is an non-volatile device option featured with separate write/read paths and large on/off ratio, etc, thus is promising for building CiM designs. In this paper, we propose a multi-bit CiM design using 2-FeFET memory that can directly perform the key multiplication and accumulation (MAC) operation of neural networks as well as more complex convolution and matrix-vector multiplication. In addition, we investigate the impact of the device non-linearity on the MAC output, and propose to use a non-linear quantization and mapping between the discharge time and the FeFET polarization state to further improve the operation linearity. Experiment results show that the proposed design can achieve desirable accuracy, with almost $6\times$ fewer transistors than 6T SRAM array, when implementing the same computation, as well as $1.42\times$ improvement in energy efficiency.

Shuo-Wei Michael Chen

Papers

A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS

In-Memory Multi-Bit Multiplication and Accumulation (MAC) Using FeFET for Energy Efficient IoT