This brief presents a low-voltage and low-noise ring voltage-controlled oscillator (VCO) where the phase noise performance is improved by reducing the total channel thermal noise injected into the output node of the VCO during the transition period of the output voltage swing. Implemented in a 65-nm CMOS technology, the proposed ring VCO operates from 485.7 to 1011.6 MHz. At 645 MHz, the measured phase noise is $-$ 110.8 dBc/Hz at an offset of 1 MHz while dissipating 10 mW from a 1-V supply.

A Low-Noise Four-Stage Voltage-Controlled Ring Oscillator in Deep-Submicrometer CMOS Technology

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for nicker (1/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator.

Phase noise and jitter in CMOS ring oscillators

Internet of Medical Things (IoMT) provides a diverse platform for healthcare to enhance the accuracy, reliability, and efficiency. In addition, it utilizes the productivity of available equipment to improve patients’ health. IoMT also provides distinct ways by which healthcare will be revolutionized as it provides numerous opportunities to handle operations with precision. However, numerous advantages have raised several security challenges, such as trust, data integrity, network constraints, and real-time processing among others. There is a requirement for a robust approach to maintain data integrity along with the behavior detection of nodes to completely maintain a secure environment. In the proposed approach, the mechanism is capable of maintaining a robust network by predicting and eliminating malicious nodes. The proposed NeuroTrust approach utilizes the trust parameters to evaluate the degree of trust that include reliability, compatibility, and packet delivery. This approach also lightens the two-way computation burden and uses a lightweight encryption mechanism to further enhance the security and integrity during data dissemination, which is required for the digital revolution in delivering efficient high quality healthcare. The performance of the proposed approach has been extensively evaluated against the absolute trust formulation, accuracy of trust computation, energy consumption, and several potential attacks. The simulation results show the effective performance to identify malicious and compromised nodes, and maintain resilience against various attacks.

NeuroTrust—Artificial-Neural-Network-Based Intelligent Trust Management Mechanism for Large-Scale Internet of Medical Things

The non-planar 3D structure of multi-gate FinFETs makes them able to be scaled down to 20 nm and beyond and also have greater performance. But any variation of the fin cross-sectional shape has an impact on the device performance. In this paper, the impact of various fin cross-sectional shape on junctionless accumulation mode bulk FinFETs with thin fins and short channel length has been evaluated. Different important device performance parameters such as ON-current (ION), OFF current (IOFF), ratio of ON/OFF current, Threshold voltage (Vth), Subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance (gm), transconductance generation factor (gm/Ids), cut-off frequency (fT), and maximum oscillation frequency (fmax) is evaluated for different fin shapes and analyzed. From the analysis, it is understood that shape of the fin cross-section has substantial impact on performance of the device. Improvement in SCEs was noticed in terms of ~ 25% reduction of DIBL and ~ 10% reduction in SS for the device with reduced fin top width. On the other hand, reduced fin top width degrades the RF performance as maximum frequency of oscillation decrease by ~ 10%. An optimal fin structure for the junctionless bulk FinFET is also obtained to have better SCEs and reasonable Analog/RF applications.

Fin shape influence on analog and RF performance of junctionless accumulation-mode bulk FinFETs

This paper investigates leakage reduction techniques for a conventional 6T SRAM cell in advanced technologies. The most promising leakage reduction techniques that have been proposed are presented and compared for the 130-nm and 65-nm technology nodes. More specifically, the impact of the evolution of the gate tunneling and substrate currents is studied considering the efficiency of those techniques. Finally, the best techniques for leakage reduction in sub 100-nm SRAM cell, and guidelines on how to merge them in order to reach an optimum, are proposed

http://ieeexplore.ieee.org/iel5/11070/34953/01669365.pdf

Impact ofCMOS Technology Scaling onSRAMStandby Leakage Reduction techniques

In complementary metal oxide semiconductor (CMOS) nanoscale technology, power dissipation is becoming important metric. In this work low leakage voltage controlled ring oscillator circuit system was proposed for critical communication systems with high oscillation frequency. An ideal approach has been presented with substrate biasing technique for reduction of power consumption. The simulation have been completed using cadence virtuoso 45 nm standard CMOS technology at room temperature 27°C with supply voltage V
 dd = 0.7 V. The simulation results suggest that voltage controlled ring oscillator has characterized with efficient low power voltage controlled oscillator (VCO) in term of minimum leakage power (1.23 nW) and maximum oscillation frequency (4.76 GHz) with joint positive channel metal oxide semiconductor and negative channel metal oxide semiconductor (PMOS and NMOS) reverse substrate bias technique. PMOS, NMOS and joint reverse body bias techniques have been compared in the presented work.

High performance of low voltage controlled ring oscillator with reverse body bias technology

We propose a FinFET based 7T and 8T Static Random Access Memory (SRAM) cells. FinFETs also promise to improve challenging performance versus power tradeoffs. Designers can run the transistors more rapidly and use the similar amount of power, compared to the planar CMOS, or run them at the similar performance using less power. The aim of this paper is to reduce the leakage current and leakage power of FinFET based SRAM cells using Self-controllable Voltage Level (SVL) circuit Techniques in 45nm Technology. SVL circuit allows supply voltage for a maximum DC voltage to be applied on active load or can reduce the supplied DC voltage to a load in standby mode. This SVL circuit can reduce standby leakage power of SRAM cell with minimum problem in terms of chip area and speed. High leakage currents in submicron regimes are primary contributors to total power dissipation of bulk CMOS circuits as the threshold voltage V th, channel length L and gate oxide thickness t ox are scaled down. The leakage current in the SRAM cell increases due to reduction in channel length of the MOSFET. Two methods are used; one method in which the supply voltage is reduced and other method in which the ground potential is increased. The Proposed FinFET based 7T and 8T SRAM cells have been designed using Cadence Virtuoso Tool, all the simulation results has been generated by Cadence SPECTRE simulator at 45nm technology.

Analysis of leakage reduction technique on FinFET based 7T and 8T SRAM cells

Priority encoder converts multiple binary inputs into binary representation of the index of active input bit with the highest priority. It is used where more than one device want to access the system, it decides the priority of the device to be serve by the system. Priority encoders are used when multiple devices have to share common resources. Several researches are made on these encoders but found no research work on FinFET based Priority encoder. The FinFET device has gained very much attention on recent VLSI designs and FinFET is the substitute for bulk CMOS at nano-scale because of its high short channel effect immunity, scalability and lower leakage power consumption. In this paper, a 4 input–3 output priority encoder is implemented using FinFET design.

Calculation of Power Delay Product and Energy Delay Product in 4-Bit FinFET Based Priority Encoder

Scaling of bulk MOSFET faces great challenges in nanoscale integration technology by producing short channel effect which leads to increased leakage. FinFET has become the most promising substitute to bulk CMOS technology because of reducing short channel effect. Dual-gate FinFET can be designed either by shorting gates on either side for better performance or both gates can be controlled independently to reduce the leakage and hence power consumption. A six transistor SRAM cell based on independent-gate FinFET technology is described in this paper for simultaneously reducing the active and standby mode power consumption. A work is focused on the independent gate FinFET technology as this mode provides less power consumption, less area consumption and low delay as compared to other modes. Leakage current and power consumption in independent gate FinFET is compared with tied gate or shorted gate FinFET SRAM cell. Moreover, delay has been estimated in presented SRAM cells. Further, leakage reduction technique is applied to independent gate FinFET 6T SRAM cell.

Analysis and design of low power SRAM cell using independent gate FinFET

In this chapter, the major enhanced techniques of internet of healthcare things (IoHT) with wearable sensor technologies (WST), stationary medical devices (SMD), and integrated system technologies (IST) for heterogeneous healthcare professionals are explored. A detailed view of the system architecture for developing IoHT device and a lot of issues are also described. The latest innovative technologies are realistic to specific purposes in the field of healthcare assessment. Analysis, sensor, and data studies approach the opportunities to improve personal healthcare and benefits for the medical industry. The ultimate aim of succeeding superior healthcare practice is to competently combine with information from diverse bases, to allocate the accumulated data, to retrieve the collected data. Effective data analysis tools from data with initialed conception services are needed while maintaining their security and privacy. Healthcare professionals, patients, and clients can take benefit of the IoHT for giving personalized smart care guidelines or solutions for existing technologies.

Shyam Akashe

Papers

High performance of low voltage controlled ring oscillator with reverse body bias technology

Analysis of leakage reduction technique on FinFET based 7T and 8T SRAM cells

Calculation of Power Delay Product and Energy Delay Product in 4-Bit FinFET Based Priority Encoder

Analysis and design of low power SRAM cell using independent gate FinFET

Feasible Challenges and Applications of IoT in Healthcare: Essential Architecture and Challenges in Various Fields of Internet of Healthcare Things