This paper introduces a novel parallel methodology for solving the spatial partitioning problem for Multi-FPGA architectures. The algorithm takes as input a HDL (Hardware Description Language) model of the application along with user specified constraints and automatically generates a task graph G; partitions G based on the user specified constraints and maps the blocks of the partitions onto the different FPGAs (Field Programmable Gate Arrays) in the given Multi-FPGA architecture, all in a single-shot. The methodology suggested in this paper makes use of an evolutionary approach for the partitioning step. The proposed algorithm was successfully employed to spatially partition a reasonably big cryptographic application that involved a 1024-bit modular exponentiation and to map the same onto a network of nine ACEX1K based Altera EP1K30QC208-1 FPGAs.

Sivaprakasam Suresh

Papers

A Parallel Evolutionary Approach to Spatial Partitioning in Reconfigurable Environments