A semiconductor integrated circuit having a two-dimensional array (MAR) and a parallel data transfer circuit (TRC) for transferring from the array data read out in parallel through data lines, in parallel to a processing circuit group (PE) by selecting the word lines of the two-dimensional memory array. The processing circuit group executing processing operations in parallel by using the data transferred from the parallel data transfer circuit. Each of the processing circuits having access to a plurality of series word lines and the data lines of the two-dimensional array through the parallel data transfer circuits. The arrangement of the parallel data transfer circuits allowing for an overlap range wherein data from each of the data lines of the memory array is available to more than one of the parallel data transfer circuits. Since the data lines of the two-dimensional memory array have the overlapped range, convolution processing operations or the like can be executed in parallel for the two-dimensional data stored in the two-dimensional memory array in a high parallelism and at a high speed.

Semiconductor IC with a plurality of processing circuits which receive parallel data via a parallel data transfer circuit

A synthetic aperture radar system (SAR) having a range correlator (10) is provided with a hybrid azimuth correlator (12) for correlation utilizing a block-pipelined Fast Fourier Transform (12a) having a predetermined FFT transform size with delay elements (Z) for so delaying SAR range correlated data as to embed in the Fourier transform operation a corner-turning function as the range correlated SAR data is converted from the time domain to a frequency domain. A transversal filter (12b) connected to receive the SAR data in the frequency domain, and from a generator (14b) a range migration compensation function, D, to a programmable shift register (30) for accurate range migration compensation; weights, W i , to multipliers (35-38) for interpolation, and an azimuth reference function, φ j , in the frequency domain to a multiplier 42 for correlation of the SAR data. Following the transversal filter is a block-pipelined inverse FFT (12c) used to restore azimuth correlated data in the frequency domain to the time domain for imaging. The FFT transform size is selected to accommodate the different SAR azimuth aperture lengths, number of looks and prefiltering requirements.

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Pipelined digital SAR azimuth correlator using hybrid FFT/transversal filter

A computation apparatus such as a Fast Fourier Transform (FFT) apparatus which processes ordered sets of data in a computation unit (4, 24) operating according to a high-speed clock includes an input buffer (1, 21) arranged to accept data in synchronism with a relatively low-speed clock, and an output buffer (6, 26) arranged to discharge the data in synchronism with the low-speed clock. The apparatus includes an internal memory (3, 23) as well as means such as selectors (2, 22) and (5, 25) for transferring data in synchronism with the high-speed clock from the input buffer to the computation unit or the memory; between the computation unit and the memory; and from the computation unit or the memory to the output buffer. The transferring means is arranged to reorder the data, preferably in reverse-digit sequence, during transfer from the input buffer or during transfer to the output buffer. This avoids the need for a separate reordering memory at the input end or output end of the device.

Computation apparatus and method

A fast Fourier transform circuit, including an illustrative radix-eight discrete Fourier transform (DFT) kernel that operates on an n-bit-serial data format, for an efficient serial-like, pipelined operation within the DFT. The circuit performs a four-point DFT on half of the input data words at a time, stores intermediate results from the four-point DFT in a commutation stage, then combines the intermediate results in two two-point DFTs. Internal multiplication in the eight-point DFT is effected in delay registers that also serve to store the intermediate results, thereby providing an economy of timing and circuit routing. Interleaving and deinterleaving operations convert the data format between three-bit-serial and conventional bit-parallel used outside the eight-point DFT kernel, which may therefore be easily cascaded for more complex FFT operations. The DFT kernel also includes means for selectively bypassing butterfly computation modules to perform shorter-length DFTs.

Fast fourier transform architecture using hybrid n-bit-serial arithmetic

A pipelined Fast Fourier Transform (FFT) architecture includes a memory for storing complex number data. A pipelined data path is coupled to the memory for accessing R complex number data therefrom, for computing an FFT butterfly, and storing R results from the FFT butterfly computation in the memory during one pipeline cycle.

Pipelined Fast Fourier Transform (FFT) architecture

A pipeline processor of a radix-2 configuration including an input, intermediate and output processing sections for performing a discrete Fourier transformation (DFT) of an input array of N signal values to derive an output array of at least N signal values representative of the frequency transformation of the input array is disclosed. The input and output processing sections include first and second pluralities of cascadedly coupled computational elements respectively, which are governed to perform computations in a pipeline fashion and to propagate resulting interelement computed signal values through the input section in a first predetermined signal flow pattern and through the output section in a second predetermined signal flow pattern to render respectively a first intermediate array and the output array of signal values. All of the multiplication processing is concentrated in the intermediate section which multiplies each of the signal values of the first intermediate array with predetermined transformation values respectively associated therewith to generate a second intermediate array of signal values which is input to the output processing section. Accordingly, the signal values of the input, first and second intermediate and output arrays are input, processed and output through top and bottom rails of the three sections of the pipeline processor sequentially in respectively corresponding predetermined orders of coupled pairs.

Smith

Papers

Multipoint pipeline processor for computing the discrete fourier transform