A scaling analysis of fundamental ESD components (low voltage transistors, N-well diodes, interconnects and thin dielectrics) for the last three CMOS technology nodes (130 nm, 90 nm and 65 nm) targeting the same low-power applications is presented. The impact of technology scaling on the ESD design window will be discussed.

Analysis of ESD protection components in 65nm CMOS technology: Scaling perspective and impact on ESD design window

We present a novel multi-RC-triggered MOSFET-based power clamp with up to 70% trigger circuit area reduction and improved transient HBM, MM, and CDM ESD clamping performance A three-stage RC-trigger circuit design gives a 300 ns self-shutdown time during power-up for mistrigger leakage current control and an improved mistrigger immunity down to 1 mus power-up rise time TLP and HBM hardware characterization data from a 90 nm CMOS technology show >5A failure current and >3 kV HBM robustness for a designed MOSFET width of 4000 mum

http://ieeexplore.ieee.org/iel5/5235855/5256743/05256781.pdf

Design and characterization of a multi-RC-triggered MOSFET-based power clamp for on-chip ESD protection

The RC-based power-rail ESD clamp circuit with the n-channel metal-oxide-semiconductor (NMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been utilized to effectively enhance the ESD robustness of CMOS ICs. In this work, a new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65 nm 1.2 V CMOS process. The layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%, as compared to the traditional RC-based ESD-transient detection circuit realized with capacitor. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long enough turn-on duration under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on event under the fast power-on and transient noise conditions.

https://ir.nctu.edu.tw:443/bitstream/11536/32011/1/000283442500026.pdf

Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection

The RC-based power-rail electrostatic-discharge (ESD) clamp circuit with big field-effect transistor (BigFET) layout style in the main ESD clamp n-channel metal-oxide-semiconductor (NMOS) transistor was widely used to enhance the ESD robustness of a CMOS IC fabricated in advanced CMOS processes. To further reduce the occupied layout area of the RC in the power-rail ESD clamp circuit, a new ESD-transient detection circuit realized with smaller capacitance has been proposed and verified in a 0.13-mum CMOS process. From the experimental results, the power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit can achieve a long-enough turn-on duration and higher ESD robustness under ESD stress condition, as well as better immunity against mis-trigger and latch-on event under the fast-power-on condition.

/pdf/area-efficient-esd-transient-detection-circuit-with-smaller-2wovov1oin.pdf

Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs

A novel clamp is presented that uses a CMOS thyristor to turn on the clamp at the ESD event. This clamp is immune to false triggering and power supply noise. Furthermore, the instability of clamps is analyzed and the new clamp is shown to have immunity to oscillation.

A transient power supply ESD clamp with CMOS thyristor delay element

A novel PMOS based power supply protection clamp is presented which is designed to operate in a state-of-the art 65 nm, low leakage CMOS process. The design is shown to be amenable to the inherent challenges posed by low cost I/O transistors. Robust ESD and electrical operation is shown as well as immunity to transient latch-up.

Smith

Papers

A low leakage low cost-PMOS based power supply clamp with active feedback for ESD protection in 65nm CMOS technologies