Soichi Inoue

TL;DR: In this paper, the correction is made on the basis of correction values calculated by a simulator and then the correction values are combined to form the corrected area. But the simulation-based correction is performed on a gate layer in a memory, while rule-based corrections are performed in the other area than the memory on the ground rules for active gate width only.

TL;DR: In this paper, a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, is presented.

TL;DR: In this paper, the correction is made on the basis of correction values calculated by a simulator and then the correction values are combined to form the corrected area. But the simulation-based correction is performed on a gate layer in a memory, while rule-based corrections are performed in the other area than the memory on the ground rules for active gate width only.

TL;DR: In this paper, an exposure apparatus for reducing/projecting a plurality of patterns of a photomask, which are elongated in at least two different directions, onto a substrate through the polygonal shape of a substrate, includes a polarized light source for illumination, a polarization control unit for changing the direction of polarization of polarized light from the polarization source, and a slit filter arranged at a position where the polarized light is focused and having a slit-like opening portion elongated.

TL;DR: In this article, a flatness evaluation method for measuring front and rear surface shapes of a wafer is described, where the wafer front surface is divided into sites, and then the flatness calculating method is selected according to a position of the site to be evaluated and flatness in the surface is acquired.