Cell phones and other portable devices are equipped with a variety of technologies by which existing functionality can be improved, and new functionality can be provided. Some relate to visual search capabilities, and determining appropriate actions responsive to different image inputs. Others relate to processing of image data. Still others concern metadata generation, processing, and representation. Yet others relate to coping with fixed focus limitations of cell phone cameras, e.g., in reading digital watermark data. Still others concern user interface improvements. A great number of other features and arrangements are also detailed.

Methods and Systems for Content Processing

A moving picture coding apparatus for performing inter-picture predictive coding for pictures constituting a moving picture is provided with a coding unit for performing predictive error coding for image data; a decoding unit for performing predictive error decoding for an output from the coding unit; a reference picture memory for holding output data from the decoding unit; and a motion vector detection unit for detecting motion vectors on the basis of the decoded image data stored in the memory. When coding a B picture as a target picture, information indicating whether or not the target picture should be used as a reference picture when coding another picture is added as header information. Therefore, in a decoding apparatus for decoding a bit stream Bs outputted from the moving picture coding apparatus, management of a memory for holding the reference picture can be facilitated on the basis of the header information.

Moving picture coding method and moving picture decoding method

A decoder decodes full frame MPEG-2 video by a single method that applies regardless of buffer memory and frame rate conversion considerations. A display control module handles frame rate and field sequence in response to host configuration, trick play command signals, and information in the received bitstream. Pictures are decoded as buffer memory for the decoded pictures becomes available, and picture display attributes are assigned and stored in a table, one string for each decoded picture. Frame rate and field sequence are managed in light of memory constraints, to produce a high quality result without re-decoding data.

Digital video decoding, buffering and frame-rate converting method and apparatus

According to some embodiments, a multithreaded microcontroller includes a thread control unit comprising thread control hardware (logic) configured to perform a number of multithreading system calls essentially in real time, e.g. in one or a few clock cycles. System calls can include mutex lock, wait condition, and signal instructions. The thread controller includes a number of thread state, mutex, and condition variable registers used for executing the multithreading system calls. Threads can transition between several states including free, run, ready and wait. The wait state includes interrupt, condition, mutex, I-cache, and memory substates. A thread state transition controller controls thread states, while a thread instructions execution unit executes multithreading system calls and manages thread priorities to avoid priority inversion. A thread scheduler schedules threads according to their priorities. A hardware thread profiler including global, run and wait profiler registers monitors thread performance to facilitate software development.

Hardware Multithreading Systems and Methods

The present invention relates to image processing apparatus and method which make it possible to prevent a decrease in compression efficiency without increasing computational complexity An intra-TP motion prediction/compensation unit 75 performs motion prediction within a predetermined search range by taking predicted motion vector information generated by an intra-predicted motion vector generating unit 76 as the center of search, on the basis of an image to be intra-predicted from a screen rearrangement buffer 62, and reference images from a frame memory 72 An inter-TP motion prediction/compensation unit 78 performs motion prediction within a predetermined search range by taking predicted motion vector information generated by an inter-predicted motion vector generating unit 79 as the center of search, on the basis of an image to be inter-encoded from the screen rearrangement buffer 62, and reference images from the frame memory 72 The present invention can be applied to, for example, an image encoding apparatus that performs encoding in H264/AVC format

Image Processing Apparatus and Method

An integrated circuit is designed by interconnecting pre-designed data-driven cores (intellectual property, functional blocks). Hardware description language (e.g. Verilog or VHDL) and software language (e.g. C or C++) code for interconnecting the cores is automatically generated by software tools from a central circuit specification. The central specification recites pre-designed hardware cores (intellectual property) and the interconnections between the cores. HDL and software language test benches, and timing constraints are also automatically generated from the central specification. The automatic generation of code simplifies the interconnection of pre-existing cores for the design of complex integrated circuits.

Automatic code generation for integrated circuit design

A system and method for decoding a video bitstream (30) and displaying (26) the video with 3:2 pull-down using a frame buffer (24) whose size is not sufficient to hold an entire decoded frame. This is accomplished by using the additional time required by the display with 3:2 pull-down to decode (12) a portion of the frame for a second time. The present invention provides memory savings, additional flexibility in decoder design, and reductions in memory controller (22) complexity and power consumption. In the case of MPEG-2 decoders, the present invention allows the implementation of PAL/SECAM main profile at main level decoders with 3:2 pull-down using only a 16 megabit memory.

Memory utilization for video decoding and display with 3:2 pull-down

Pre-designed and verified data-driven hardware cores (intellectual property, functional blocks) are assembled to generate large systems on a single chip. Token transfer between cores is achieved upon synchronous assertion, over dedicated connections, of a one-bit ready signal by the transmitter and a one-bit request signal by the receiver. The ready-request signal handshake is necessary and sufficient for token transfer. There are no combinational paths through the cores, and no latches or master controller are used. The architecture and interface allow a significant simplification in the design and verification of large systems integrated on a single chip.

Data flow integrated circuit architecture

According to some embodiments, a multithreaded microcontroller includes a thread control unit comprising thread control hardware (logic) configured to perform a number of multithreading system calls essentially in real time, e.g. in one or a few clock cycles. System calls can include mutex lock, wait condition, and signal instructions. The thread controller includes a number of thread state, mutex, and condition variable registers used for executing the multithreading system calls. Threads can transition between several states including free, run, ready and wait. The wait state includes interrupt, condition, mutex, I-cache, and memory substates. A thread state transition controller controls thread states, while a thread instructions execution unit executes multithreading system calls and manages thread priorities to avoid priority inversion. A thread scheduler schedules threads according to their priorities. A hardware thread profiler including global, run and wait profiler registers is used to monitor thread performance to facilitate software development.

Sorin C. Cismas

Papers

Hardware Multithreading Systems and Methods

Automatic code generation for integrated circuit design

Memory utilization for video decoding and display with 3:2 pull-down

Data flow integrated circuit architecture

Hardware multithreading systems with state registers having thread profiling data