An apparatus and method for disk mapping and data retrieval includes a data storage medium on which has been stored a plurality of data records. Each record includes at least a record identification portion, for uniquely identifying each record from among the plurality of data records. The apparatus builds a record locator table and high speed semiconductor memory which comprises the unique record identifiers for the records on the storage medium as well as a record locator index generated by the apparatus, which indicates the address of the data record on the storage medium. Data retrieval is facilitated by first searching the record locator table in high speed semiconductor memory for a requested data record. Utilizing the record locator index associated with the reqested data record, the system directly accesses the requested data record on the storage medium thereby minimizing storage medium search time. Also disclosed is an apparatus and method for converting CKD formatted data records to FBA formatted disk drives and for building and compressing the "count" portion of the CKD data formatted record into a record locator table.

System and method for disk mapping and data retrieval

A fault-tolerant storage device array using a copyback cache storage unit for temporary storage. When a Write occurs to the RAID system, the data is immediately written to the first available location in the copyback cache storage unit. Upon completion of the Write to the copyback cache storage unit, the host CPU is immediately informed that the Write was successful. Thereafter, further storage unit accesses by the CPU can continue without waiting for an error-correction block update for the data just written. In a first embodiment of the invention, Read-Modify-Write operations are performed during idle time. In a second embodiment of the invention, normal Read-Modify-Write operation by the RAID system controller continue use Write data in the controller's buffer memory. In a third embodiment, at least two controllers, each associated with one copyback cache storage unit, copy Write data from controller buffers to the associated copyback cache storage unit. If a copyback cache storage unit fails, more than one controller share a single copyback storage unit. In a fourth embodiment, Write data is copied from a controller buffer to a reserved area of each storage unit comprising the array.

Storage device array architecture with copyback cache

The present invention is drawn to a hybrid data reconstruction system and method for a data storage device. Data is selectively stored according to one of two or more redundancy schemes such that critical data is stored according to a scheme which has a higher degree of redundancy.

Hybrid data storage and reconstruction system and method for a data storage device

A method for recovering data from a cache memory of a second storage controller by access to a cache memory of a first storage controller is presented. The storage controllers are coupled by a private common data path. The method includes copying metadata corresponding to the data stored in the cache memory of the second storage controller to the cache memory of the first storage controller through the private common data path. The metadata may include pointers to and the size of the data. After copying the metadata pointers, the data in the cache memory of the second storage controller is established in the cache memory of the first storage controller. As a result, the entire set of data does not need to be totally recovered to the hard disk before resuming host communications in a recovery operation, which may take a relatively long time. Instead, if a controller fails, only a portion of the data in the cache of the failed controller, the data describing the recovery information, needs to be incorporated into the "dirty" cache of the remaining controller before communications with the host are resumed.

Quick recovery of write cache in a fault tolerant I/O system

A magnetic disk controller incorporating a cache memory which employs an LRU (Least Recently Used) scheme in a replacement algorithm of cache blocks and comprising a directory memory whose entries have LRU counter fields, a host system issuing a read/write command to which an arbitrary LRU settling value is appended, a directory search circuit, and a microprocessor. The directory search circuit searches the directory memory in response to the read/write command issued from the host system. The microprocessor stores the LRU setting value appended to the read/write command in the LRU counter field of the hit entry of the directory memory or of the entry corresponding to the repalacement target cache block, in response to the search result of the directory search circuit.

Cache system used in a magnetic disk controller adopting an LRU system

In response to a command including file extent information defining a file area received from a host processor, a disk cache processor stores the file extent information in an extent table and reserves a corresponding area in a disk cache buffer. In response to a WRITE command, the processor stores the data in the corresponding reserved area of the disk cache buffer and sets a write flag of the corresponding entry of a cache directory. When the processor is idling, it writes to a disk unit the data in the disk cache buffer which has not yet been written to the disk unit, and resets the corresponding write flag. In response to a command received from the host processor which has file extent information and designates a logical termination of a program, the processor writes all of the not-yet-written data which corresponds to the file area indicated by the extent information. When an error is caused during data write to the disk unit, the processor stores corresponding error status information into an error log table such that it corresponds to the extent information in the extent table. After data write into the designated area is terminated, the processor fetches the error status information for this file area alone and transfers the fetched information to the host processor.

Sotaro Ushiro

Papers

Disk cache system