In this paper we present DRAMSim2, a cycle accurate memory system simulator. The goal of DRAMSim2 is to be an accurate and publicly available DDR2/3 memory system model which can be used in both full system and trace-based simulations. We describe the process of validating DRAMSim2 timing against manufacturer Verilog models in an effort to prove the accuracy of simulation results. We outline the combination of DRAMSim2 with a cycle-accurate x86 simulator that can be used to perform full system simulations. Finally, we discuss DRAMVis, a visualization tool that can be used to graph and compare the results of DRAMSim2 simulations.

DRAMSim2: A Cycle Accurate Memory System Simulator

In this paper, we explore the possibility of using STT-RAM technology to completely replace DRAM in main memory. Our goal is to make STT-RAM performance comparable to DRAM while providing substantial power savings. Towards this goal, we first analyze the performance and energy of STT-RAM, and then identify key optimizations that can be employed to improve its characteristics. Specifically, using partial write and row buffer write bypass, we show that STT-RAM main memory performance and energy can be significantly improved. Our experiments indicate that an optimized, equal capacity STT-RAM main memory can provide performance comparable to DRAM main memory, with an average 60% reduction in main memory energy.

/pdf/evaluating-stt-ram-as-an-energy-efficient-main-memory-4wedplgtre.pdf

Evaluating STT-RAM as an energy-efficient main memory alternative

Main memory is responsible for a large and increasing fraction of the energy consumed by servers. Prior work has focused on exploiting DRAM low-power states to conserve energy. However, these states require entire DRAM ranks to be idled, which is difficult to achieve even in lightly loaded servers. In this paper, we propose to conserve memory energy while improving its energy-proportionality by creating active low-power modes for it. Specifically, we propose MemScale, a scheme wherein we apply dynamic voltage and frequency scaling (DVFS) to the memory controller and dynamic frequency scaling (DFS) to the memory channels and DRAM devices. MemScale is guided by an operating system policy that determines the DVFS/DFS mode of the memory subsystem based on the current need for memory bandwidth, the potential energy savings, and the performance degradation that applications are willing to withstand. Our results demonstrate that MemScale reduces energy consumption significantly compared to modern memory energy management approaches. We conclude that the potential benefits of the MemScale mechanisms and policy more than compensate for their small hardware cost.

MemScale: active low-power modes for main memory

DRAM vendors have traditionally optimized the cost-per-bit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, where a single request activates thousands of bit-lines in many DRAM chips, only to return a single cache line to the CPU. The focus on cost-per-bit is questionable in modern-day servers where operating costs can easily exceed the purchase cost. Modern technology trends are also placing very different demands on the memory system: (i)queuing delays are a significant component of memory access time, (ii) there is a high energy premium for the level of reliability expected for business-critical computing, and (iii) the memory access stream emerging from multi-core systems exhibits limited locality. All of these trends necessitate an overhaul of DRAM architecture, even if it means a slight compromise in the cost-per-bit metric. This paper examines three primary innovations. The first is a modification to DRAM chip microarchitecture that re tains the traditional DDRx SDRAMinterface. Selective Bit-line Activation (SBA) waits for both RAS (row address) and CAS (column address) signals to arrive before activating exactly those bitlines that provide the requested cache line. SBA reduces energy consumption while incurring slight area and performance penalties. The second innovation, Single Subarray Access (SSA), fundamentally re-organizes the layout of DRAM arrays and the mapping of data to these arrays so that an entire cache line is fetched from a single subarray. It requires a different interface to the memory controller, reduces dynamic and background energy (by about 6X), incurs a slight area penalty (4%), and can even lead to performance improvements (54% on average) by reducing queuing delays. The third innovation further penalizes the cost-per-bit metric by adding a checksum feature to each cache line. This checksum error-detection feature can then be used to build stronger RAID-like fault tolerance, including chipkill-level reliability. Such a technique is especially crucial for the SSA architecture where the entire cache line is localized to a single chip. This DRAM chip microarchitectural change leads to a dramatic reduction in the energy and storage overheads for reliability. The proposed architectures will also apply to other emerging memory technologies (such as resistive memories) and will be less disruptive to standards, interfaces, and the design flow if they can be incorporated into first-generation designs.

/pdf/rethinking-dram-design-and-organization-for-energy-369m9iiq1o.pdf

Rethinking DRAM design and organization for energy-constrained multi-cores

To increase datacenter energy efficiency, we need memory systems that keep pace with processor efficiency gains. Currently, servers use DDR3 memory, which is designed for high bandwidth but not for energy proportionality. A system using 20% of the peak DDR3 bandwidth consumes 2.3x the energy per bit compared to the energy consumed by a system with fully utilized memory bandwidth. Nevertheless, many datacenter applications stress memory capacity and latency but not memory bandwidth. In response, we architect server memory systems using mobile DRAM devices, trading peak bandwidth for lower energy consumption per bit and more efficient idle modes. We demonstrate 3-5x lower memory power, better proportionality, and negligible performance penalties for datacenter workloads.

/pdf/towards-energy-proportional-datacenter-memory-with-mobile-2oz70z29fp.pdf

Towards energy-proportional datacenter memory with mobile DRAM

Is your memory hierarchy stopping your microprocessor from performing at the high level it should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem. The book tells you everything you need to know about the logical design and operation, physical design and operation, performance characteristics and resulting design trade-offs, and the energy consumption of modern memory hierarchies. You learn how to to tackle the challenging optimization problems that result from the side-effects that can appear at any point in the entire hierarchy.As a result you will be able to design and emulate the entire memory hierarchy. . Understand all levels of the system hierarchy -Xcache, DRAM, and disk. . Evaluate the system-level effects of all design choices. . Model performance and energy consumption for each component in the memory hierarchy.

Memory Systems: Cache, DRAM, Disk

A hybrid disk drive, i.e., a disk drive with two types of permanent storage media (conventional disk media and nonvolatile memory, such as flash memory), uses its nonvolatile memory in operational modes other than the power-save or "standby" mode wherein the disks are spun down. In a first additional mode, called a "performance" mode, one or more blocks of write data are destaged from volatile memory (the disk drive's write cache) and written to the disk and simultaneously one or more data blocks of write data are destaged from the volatile memory and written to the nonvolatile memory. In a second additional mode, called a "harsh-environment" mode, the disk drive includes one or more environmental sensors, such as temperature and humidity sensors, and the nonvolatile memory temporarily replaces the disks as the permanent storage media. In a third additional mode, called a "write-inhibit" mode, the disk drive includes one or more write-inhibit detectors, such as a shock sensor for detecting disturbances and vibrations to the disk drive. In write-inhibit mode, if the write-inhibit signal is on then the write data is written from the volatile memory to the nonvolatile memory instead of to the disks.

Disk drive with nonvolatile memory having multiple modes of operation

A mobile computing hard disk drive has both a flash memory device and a DRAM device, with the HDD controller managing data storage between disk, DRAM, and flash both when write requests arrive and when the HDD is idle to optimize flash memory device life and system performance.

HDD having both dram and flash memory

A disk drive that includes nonvolatile memory monitors the drive's reliability-related parameters to detect real or potential failure events, and records failure-related data in nonvolatile memory, rather than in reserved areas of the disks. The monitoring may be by running a diagnostic routine or by regular or periodic monitoring of disk drive sensors, like temperature and shock sensors. The failure events to be monitored and recorded may include defective data sectors. When a new defective sector is detected after the disk drive has been put into operation, that defective sector is taken out of service and its logical block address (LBA) is mapped to a memory space in the nonvolatile memory rather to a reserved spare sector on the disk. When a read or write command is received for an LBA range that includes the defective sector's LBA, the defective sector is skipped while the whole LBA range of the command is processed and the user data for the defective sector's LBA is read from or written to the mapped memory space in the nonvolatile memory.

Disk drive with nonvolatile memory for storage of failure-related data

A RAID subsystem with a plurality of hard disk drives has each disk controller autonomously executing data scrubbing on its disks instead of requiring the RAID controller to execute data scrubbing. The data scrubbing may be interrupted upon an I/O request from the RAID controller, or it may continue if a guaranteed scrub rate is not being achieved. Data is stored in large bands of concentric data tracks, and a band may be preferentially selected for scrubbing based on frequency of reading the band, or recency of writing to the band.

Spencer W. Ng

Papers

Memory Systems: Cache, DRAM, Disk

Disk drive with nonvolatile memory having multiple modes of operation

HDD having both dram and flash memory

Disk drive with nonvolatile memory for storage of failure-related data

System and method for autonomous data scrubbing in a hard disk drive