New memristor-less, resistor-less, two-OTA based grounded and floating meminductor emulators and their applications in chaotic oscillators

In this paper, an optimized memristor emulator circuit is designed, by using nine MOSFET transistors and a ground capacitor. Our area- and power-optimized emulator circuit can be used for basic data storage and processing at the monitoring edge, in real-time applications. The memristor shows a nonlinear voltage–current relationship, but no multiplier circuit provides the memristor’s nonlinear characteristics. As a result, the proposed memristor emulator has a very low chip area. The memristor circuit is designed in LTSpice, using 16 nm and 45 nm CMOS technology parameters, and the operating voltage is ±0.9 V. In this research, the theoretical derivations are validated using the simulated results of the memristor emulator circuit using different frequencies, capacitors, and input voltages in SPICE simulations.

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CMOS-Based Memristor Emulator Circuits for Low-Power Edge-Computing Applications

Current biomedical applications are using numerous wired and wireless sensors that keep track of various biological signals. These signals are continuously tracked, processed, and monitored for different biomedical applications. In this process, power consumption of the sensor is one of the important parameters to investigate. Most of the signal processing mechanisms is performed in mobile or computer-based applications. But data conversion and transfer can only be performed in sensor hardware where basic arithmetic operations are evaluated on voltages or current values. This work make use of a new and simple method to perform analog arithmetic operations, in which signals are interpreted and also stored using the memristor, rather than voltage or current. A new circuit is also being developed for programming the memristor's memristance with a predetermined analog value. The power dissipated by CMOS EX-NOR gate is highest, the power dissipated by memristor NOR gate is least. This paper will use the LTspice simulator, a common version of SPICE, to address memristor behavior.

Design of Memristor Based Logic Gates for Low Power Wireless Sensors in Biomedical Applications

The static random access memory (SRAM) Array is used in applications such as cache memories, microprocessors, and portable devices such as smart watches and mobile phones. As technology advances to the submicron level, power dissipation becomes a major disadvantage in SRAM cells, necessitating the development of low-power applications. As a result, it's important to design a memory that consumes less power. The main motive of this paper is to design 4*4, 8*8, and 16*16 SRAM array using 6T and 7T SRAM cells using Graphene Nano Ribbon Field Effect Transistor (GNRFET) technology and compare power dissipation between Complementary Metal Oxide Semiconductor (CMOS) and GNRFET technologies. The MOS-GNRFET HSPICE libraries in HSPICE TOOL is used to perform transient analysis for the Read and Write operations.

Sravanth Kumar R

Papers

Design of Memristor Based Logic Gates for Low Power Wireless Sensors in Biomedical Applications

Design and Comparison of Advanced Low Power SRAM Cells using GNRFET Technology