Showing papers by "Sri Parameswaran published in 1994"
01 May 1994
TL;DR: A tool which converts standard C code into an equivalent VHDL behavioural description is presented, used to generate a chip-level hardware interconnect of identical functionality to the original C code.
Abstract: Automation of the hardware/software codesign methodology brings with it the need to develop sophisticated high-level synthesis tools. This paper presents a tool which is the result of such development. This tool converts standard C code into an equivalent VHDL behavioural description. This description is used to generate a chip-level hardware interconnect of identical functionality to the original C code. >
9 citations
TL;DR: A set of fast algorithms are presented here for the selection of components that map each of these abstract building blocks to one of a number of suitable physical components.
Abstract: The specification of a synchronous circuit can be given as a set of abstract building blocks that are interconnected. A set of fast algorithms are presented here for the selection of components that map each of these abstract building blocks to one of a number of suitable physical components. The first set of algorithms select the set of fastest or cheapest (smallest area) of all possible components. Another set of algorithms is given that will find a solution with user-defined constraints. These algorithms, which are implemented as part of the SPOT system, use a exhaustive list of timing information to increase the likelihood of a good solution. >
3 citations
Journal Article•
TL;DR: Jha et al. as discussed by the authors proposed a method for resynthesizing the controller of a design for a fixed datapath with the objective of increasing the design's throughput by minimizing its total execution time.
Abstract: Author(s): Jha, Pradip K.; Parameswaran, Sri; Dutt, Nikil D. | Abstract: In this report we describe a method for resynthesizing the controller of a design for a fixed datapath with the objective of increasing the design's throughput by minimizing its total execution time. This work has tremendous potential in two important areas: one, design reuse for retargetting datapaths to new libraries, new technologies and different bit-widths; and two, back-annotation of physical design information during High-level Synthesis (HIS), and subsequent adjustment of the design’s schedule to account for realistic physical design information with minimal changes to the datapath. We present our approach using various formulations, prove optimality of our algorithm and demonstrate the effectiveness of our technique on several HIS benchmarks. We have observed improvements of up to 36% in execution time after straightforward application of our controller resynthesis technique to the outputs of HIS.
2 citations
25 Apr 1994
TL;DR: The TSC/CD and SFS/SCD models are based on two new proposed low-cost, modular, totally self checking, edge triggered and error propagating (code disjoint) flip-flops.
Abstract: Introduces design models for totally self checking, code disjoint (TSC/CD) and strongly fault secure, strongly code disjoint (SFS/SCD) synchronous controllers. The TSC/CD and SFS/SCD models are based on two new proposed low-cost, modular, totally self checking (TSC), edge triggered and error propagating (code disjoint) flip-flops; one, a D flip-flop which can be used in TSC and strongly fault secure (SFS) synchronous circuits with two-rail codes; the other a T flip-flop, used in a similar way as the D flip-flop but retaining the error as an indicator until the next presetting, as an aid to error propagation. >
2 citations
23 Sep 1994
TL;DR: The CAD tools developed are used to design Strongly Fault Secure, Strongly Code Disjoint (SFS/SCD) and Totally Self Checking, Code Disjoined (TSC/CD) circuits and the output is given in structural level VHDL which can be synthesized via commercial tools.
Abstract: In this paper we explain the steps of the CAD tools developed for self checking circuits. The CAD tools developed are used to design Strongly Fault Secure, Strongly Code Disjoint (SFS/SCD) and Totally Self Checking, Code Disjoint (TSC/CD) circuits. Self checking combinatorial and sequential synchronous circuits including shift registers, counters, adders and checkers are designed, using these tools. The output of these CAD tools is given in structural level VHDL which can be synthesized via commercial tools.
1 citations