VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

In order to ensure trusted in---field operation of integrated circuits, it is important to develop efficient low---cost techniques to detect malicious tampering (also referred to as Hardware Trojan ) that causes undesired change in functional behavior Conventional post--- manufacturing testing, test generation algorithms and test coverage metrics cannot be readily extended to hardware Trojan detection In this paper, we propose a test pattern generation technique based on multiple excitation of rare logic conditions at internal nodes Such a statistical approach maximizes the probability of inserted Trojans getting triggered and detected by logic testing, while drastically reducing the number of vectors compared to a weighted random pattern based test generation Moreover, the proposed test generation approach can be effective towards increasing the sensitivity of Trojan detection in existing side---channel approaches that monitor the impact of a Trojan circuit on power or current signature Simulation results for a set of ISCAS benchmarks show that the proposed test generation approach can achieve comparable or better Trojan detection coverage with about 85% reduction in test length on average over random patterns

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MERO: A Statistical Approach for Hardware Trojan Detection

A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Method for fabrication of a semiconductor device and structure

Logic fault diagnosis or fault isolation is the process of analyzing the failing logic portions of an integrated circuit to isolate the cause of failure. Fault diagnosis plays an important role in multiple applications at different stages of design and manufacturing. A logic diagnosis tool with applicability to a spectrum of logic DFT, ATPG and test strategies including full/almost fullscan circuits with combinational ATPG, partial-scan and non-scan circuits with sequential ATPG and to functional patterns in general is presented. Novel features incorporated into the tool include static and dynamic structural processing for partial-scan circuits, windowed fault simulation, and diagnostic models for open defects and cover algorithms for multiple fault diagnosis. Experimental results include simulation results on processor functional blocks and silicon results on chipsets and processors from artificially induced defects and production fallout.

POIROT: a logic fault diagnosis tool and its applications

In this paper, we present a scan chain fault diagnosis procedure. The diagnosis for a single scan chain fault is performed in three steps. The first step uses special chain test patterns to determine both the faulty chain and the fault type in the faulty chain. The second step uses a novel procedure to generate special test patterns to identify the suspect scan cell within a range of scan cells. Unlike previously proposed methods that restrict the location of the faulty scan cell only from the scan chain output side, our method restricts the location of the faulty scan cell from both the scan chain output side and the scan chain input side. Hence the number of suspect scan cells is reduced significantly in this step. The final step further improves the diagnostic resolution by ranking the suspect scan cells inside this range. The proposed technique handles both stuck-at and timing failures (transition faults and hold time faults). The extension of the procedure to diagnose multiple faults is discussed. The experimental results show the effectiveness of the proposed method.

A technique for fault diagnosis of defects in scan chains

Debug of at-speed failures using functional tests is a key challenge as part of frequency pushes during post-silicon debug to improve performance of high performance designs, especially microprocessors. In this paper, we present a technique to automate the debug of speed path failures using failing functional tests by extracting information from design-for-debug features and then algorithmically isolating the internal speed-paths that could be the source of the failures. Results from application of the technique during silicon debug on the Intel ® Core ™ i7 quad-core processor is presented.

Automated Debug of Speed Path Failures Using Functional Tests

This paper studies the impact of N-detect scan ATPG patterns on test quality and associated test costs. An incremental method for test generation is presented. Metrics to evaluate the richness of the test set are presented. The natural N-detect profiles of regular one-detect test sets and the impact to test data volume and test time of generating additional patterns is studied. Results are presented on an lntel/spl reg/ Pentium/spl reg/ 4 processor. Simulation results from evaluating the patterns on layout extracted and random bridges are presented. Silicon data from production test shows the effectiveness of N-detect tests.

An experimental study of N-detect scan ATPG patterns on a processor

A technique to perform logic diagnosis of defects that cause interconnects in a digital logic circuit to become open or highly resistive is presented. The novel features of this work include a diagnostic fault model to capture potential faulty behaviors in the presence of an open defect and diagnosis algorithms that leverage the diagnostic model while circumventing the need for detailed circuit-level (SPICE) simulation and extraction of parasitic capacitance. Other aspects of the technique include a path-tracing procedure to limit the number of interconnects that need to be analyzed and extensions for multiple defects. Experimental results include simulation results on processor functional blocks and silicon results on a chipset from artificially induced defects and production fallout.

Srikanth Venkataraman

Papers

POIROT: a logic fault diagnosis tool and its applications

A technique for fault diagnosis of defects in scan chains

Automated Debug of Speed Path Failures Using Functional Tests

An experimental study of N-detect scan ATPG patterns on a processor

A technique for logic fault diagnosis of interconnect open defects