A compact analog-to-digital converter (ADC) system suitable for high-resolution gamma-ray detectors has been developed around the Burr Brown PCM78P 16-b audio ADC. An associated application-specific integrated circuit (ASIC), handling four ADCs, provides sliding scale circuitry, lower threshold adjustment, channel number identification, and zero suppression. The conversion time is 4.5 mu s, and the differential nonlinearity, for 13-b resolution, is less than +or-0.8%. >

Analog to digital converter

A novel method of adapting Fibonacci number weighting to raw binary code data of variable length to use the code as a fixed length code by using only those code sequences with a fixed number of cells rather than a fixed number of bits, converting the code to a continuous numerical sequence useful particularly for linear media and data transmission. Encoder and decoder systems useful to enable storing or recording and reading or utilization of the Fibonacci code in bar code, magnetic and other media.

Method of fixed-length binary encoding and decoding and apparatus for same

A method for numerical representation particularly advantageously applicable to storage of data and to transmit and receive operations of signals modulated by digital data and adapted to minimize by a selective rate the data amount, under maintainment of their integrity.

Method for numeric compression and decompression of binary data

An encoding arrangement for encoding a sequence of (n-1)-bit information words into a sequence of n-bit channel words is disclosed, comprising input means (1) for receiving the information words, converter means (2) for converting the (n-1)-bit information words into n-bit channel words and output means (3) for supplying the channel words. The converter means (2) comprises weight vector coefficient supply means (7) for supplying a weight vector w, the weight vector having n weight vector coefficients wi, where i is an integer running from 1 to n and the weight vector coefficients being in the form of (n-1)-bit binary words, and calculation means (5) for carrying out a calculation using an information word so as to obtain a channel word, which calculation is based on the following steps: (a) set a running parameter j equal to n; (b) determine whether the value of the information word is larger than or equal to the weight vector coefficient wj, if so, set the binary value in the bit position j of the channel word to 'zero' and subtract the value of the weight coefficient wj from the value of the information word so as to obtain a new value for the information word, if not, set the said binary value to 'one'; (c) repeat the step (b) n-1 times for each next lower value for j, wn being the weight vector coefficient having the largest value and weight vector coefficients having a next lower subscript j having a smaller value, and n is an integer constant. In accordance with the invention, the weight vector coefficient supply means (7) is adapted to supply only p bits of a weight vector coefficient wi, the remaining n-1-p bits of the (n-1)-bit weight vector coefficient word being 'zeroes' to be added before or after the p-bit binary word or before and after the p-bit binary word so as to obtain said weight vector coefficient, and that p is an integer smaller than n-1.

Encoding arrangement for encoding a sequence of (n-1)-bit information words into a sequence of n-bit channel words, and a decoding arrangement for decoding a sequence of n-bit channel words into a sequence of (n-1) bit information words

A circuit embodied in an integrated circuit is characterized by an architecture having a minimal depth defined by a recursive expansion of output functions h_n=OR(h_k, AND(v_k, h_{n−k})) and v_n=AND(v_k, v{n−k}), where k=F_l and n−k=F_{l−1}, satisfies F_l<n=F_{l+1}, {F_l} is a Fibonacci series and n is the number of bits of an input to the circuit. In one form, the circuit is a comparator having output functions h_n and v_n that depend from input functions U[i]=AND(NOT(A[i]), B[i]) and V[i]=OR(NOT(A[i]), B[i]), where A[i] and B[i] are inputs to the comparator, and functions h_n, v_n defined as h_n=h_n(U[ 0 ], U[ 1 ], V[ 1 ], . . . , U[n−1], V[n−1])=OR(U[n−1], AND(V[n−1], U[n−2]), . . . , AND(V[n−1], . . . , V[ 1 ], U[ 0 ])), and v_n=v_n(V[ 0 ], . . . , V[n− 1 ])=AND(V[ 0 ], . . ., V[n−1]). In one form, the comparator includes an LEQ input that identifies strict or non-strict inequality comparison by the comparator. The depth is further minimized by a distribution of negations of elements forming the circuit. A computer process is described to carry out the design, including mapping 2-input elements from a cell library of 3-input elements.

Optimization of comparator architecture

An arrangement for reduction of Fibonacci p-codes to minimal form, which performs, in succession, all convolutions and all devolutions of bits of the original Fibonacci p-code of a number, whereto the original combination of binary signals corresponds. The original combination of binary signals is handled during the convolution operation so that a binary signal corresponding to a 0 value of the lth digit of the original Fibonacci p-code of the number, as well as binary signals corresponding to l values of the (l - i)th and the (l - p- 1)th digit of the original Fibonacci p-code of the number, are substituted by their inverse signals. The original combination of binary signals is handled during the devolution operation so that a binary signal corresponding to a 1 value of the lth digit of the original Fibonacci p-code of the number, as well as binary signals corresponding to 0 values of the digits (l - p) through (l - 2p), inclusive, of the original Fibonacci p-code of the number, are substituted by their inverse signals.

Method and device for reduction of fibonacci p-codes to minimal form

Einrichtung zur reduzierung von fibonacci-p-codes auf die minimalform

Ce dispositif comporte n cellules fonctionelles 2 de meme type; la l-ieme cellule 2 a sa sortie de convolution reliee a l'une des entrees de prepositionnement de convolution 5 de la (l-1)-ieme cellule et a l'autre entree de prepositionnement de convolution 6 de la (l-p-1)-ieme cellule, l'une des entrees d'information de convolution 3 etant reliee a la sortie d'information de la (l-l)-ieme cellule 2, l'autre entree d'information 4 etant reliee a la sortie d'information de la (l-p1)-ieme 2 et a l'une des entrees 3 de la (l-1)-ieme cellule, les entrees de commande de convolution 7 de la totalite des cellules 2 etant reunies en un point commun pour former l'entree de commande de convolution du dispositif 1, les n entrees d'information 8 et les n sorties d'information des cellules formant respectivement l'entree d'information et la sortie d'information a plusieurs bits du dispositif 1.

Dispositif pour la reduction des codes p de fibonacci a la forme minimale

Fibonacci-to-binary code converter

FIELD: computer equipment.SUBSTANCE: invention relates to automation and computer equipment. Digital linear interpolator contains coordinate increment registers, adder, matching blocks, blocks for analyzing the difference in coordinate increments, block for analyzing the sign of the evaluation function, register for the difference in coordinate increments, while the binary digit of all blocks is increased by one by adding the lower (n + 1)th digit.EFFECT: technical result is higher accuracy of interpolation.1 cl, 1 dwg

Stakhov Aleksej P

Papers

Method and device for reduction of fibonacci p-codes to minimal form

Einrichtung zur reduzierung von fibonacci-p-codes auf die minimalform

Dispositif pour la reduction des codes p de fibonacci a la forme minimale

Fibonacci-to-binary code converter

Digital linear interpolator