Due to the significant contribution of interconnect to the area and speed of today's circuits
and the technological trend toward smaller and faster gates which will make the effects of
interconnect even more substantial, interconnect optimization must be performed during all
phases of the design. The premise of this paper is that by increasing the interaction between
logic synthesis and physical design, circuits with smaller area and interconnection length,
and improved performance and routability can be obtained compared to when the two processes
are done separately. In particular, this paper describes an integrated approach to
technology mapping and physical design which finds solutions in both domains of design
representation simultaneously and interactively. The two processes are performed in lockstep:
technology mapping takes advantage of detailed information about the interconnect
delays and the layout cost of various optimization alternatives; placement itself is guided by
the evolving logic structure and accurate path-based delay traces. Using these techniques,
circuits with smaller area and higher performance have been synthesized.

/pdf/combining-technology-mapping-with-layout-49yxok6w12.pdf

Stefan Mayrhofer

Papers

A Flow-Oriented Approach to the Placement of Boolean Networks.