S
Stephen F. Heil
Researcher at Microsoft
Publications - 24
Citations - 3141
Stephen F. Heil is an academic researcher from Microsoft. The author has contributed to research in topics: Hardware acceleration & Component (UML). The author has an hindex of 13, co-authored 24 publications receiving 2679 citations. Previous affiliations of Stephen F. Heil include Unisys.
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Patent
Data processing system having a hardware acceleration plane and a software plane
TL;DR: In this paper, a data processing system is described that includes two or more software-driven host components, which collectively provide a software plane and hardware acceleration components, such as FPGA devices, provide a hardware acceleration plane.
Patent
Locally restoring functionality at acceleration components
Stephen F. Heil,Sitaram Lanka,Adrian M. Caulfield,Eric S. Chung,Andrew Putnam,Douglas C. Burger,Yi Xiao +6 more
TL;DR: A role can be locally restored at an acceleration component when an error is self-detected at the acceleration component (e.g., by local monitoring logic). Locally restoring a role can include resetting internal state (application logic) of the component providing the role.
Patent
Implementing a Service Using Plural Acceleration Components
TL;DR: In this article, a data processing system is described that includes two or more software-driven host components that collectively provide a software plane, which includes one or more services, including at least one multi-component service.
Patent
Allocating acceleration component functionality for supporting services
TL;DR: In this paper, a service manager uses a finite number of acceleration components to accelerate services, and the acceleration components can be allocated in a manner that balances load in a hardware acceleration plane, minimizes role switching, and adapts to demand changes.
Patent
Providing services in a system having a hardware acceleration plane and a software plane
TL;DR: In this paper, a service mapping component (SMC) is described for allocating services to hardware acceleration components in a data processing system based on different kinds of triggering events, where each host component in the software plane is then configured to access the service on one or more of the selected hardware acceleration component(s) via an associated local HPC component, or via some other route.