An integrated VCO having an improved tuning range over process and temperature variations. There is therefore provided in a present embodiment of the invention an integrated VCO. The VCO comprises, a substrate, a VCO tuning control circuit responsive to a VCO state variable that is disposed upon the substrate, and a VCO disposed upon the substrate, having a tuning control voltage input falling within a VCO tuning range for adjusting a VCO frequency output, and having its tuning range adjusted by the tuning control circuit in response to the VCO state variable.

Integrated VCO having an improved tuning range over process and temperature variations

A phase lock loop circuit 60 has a phase frequency detector 62 , a charge pump 64 , an active filter 87 and a voltage-controlled oscillator 100 . The phase detector generates UP and DN signals indicative of the relative frequency of F R , a reference signal, and F V , a signal controlled by the voltage-controlled oscillator. A charge pump using logic gates (buffer 66 and inverter 68 ) to produce a voltage drop over resistors 74 and 84 to generate a voltage at a node coupled to the input of transmission gate 76 according to the values of the UP and DN signals. When the transmission gate 76 is closed (low impedance) the charge pump may sink or source current to the inverting input of the operational amplifier 86 of the active filter 86 . When the transmission gate is open (high impedance state) the inverting input is electrically isolated from the node.

Charge pump phase locked loop

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

System and method for providing a low power receiver design

Fully integrated tuner architecture

System and method for on-chip filter tuning

A Phase Locked Loop (PLL) circuit includes a control signal generator, a digital phase detector, logic gates, a charge pump (charge/discharge circuit), a transmission gate, a loop filter, a lead-lag filter and a voltage controlled oscillator (VCO). Outputs of the digital phase detector are coupled through the logic gates to inputs of the charge pump. An output of the charge pump is coupled to the capacitor and to a first input/output of the transmission gate. A second input/output of the transmission gate is coupled to an input of the loop filter whose output is coupled to an input of the VCO whose output is coupled to a first input of the digital phase detector. A second input of the digital phase detector is coupled to a source of a reference frequency signal. The control signal generator generates non-overlapping complementary control signals with one of same connected to the logic gates and the other connected to the transmission gate. Accordingly, the electrical path from the digital phase detector to the charge pump through the logic gates is closed and the electrical path from the capacitor to the loop filter is open or vice versa. The loop filter includes an operational amplifier with AC feedback which is controlled by the same signal which controls the logic gates. The PLL circuit is typically formed on a single integrated circuit silicon chip using CMOS technology.

Phase locked loop circuit with digital control

A method for tuning and aligning an electronically tuned FM broadcast receiver is described. The system described compensates for the mismatch of component values between the antenna and RF amplifier tuned circuits, and the IF offset between the local oscillator frequency and the center frequencies of the antenna and RF resonant circuits by developing independent tuning signals for the circuits. The system also provides temperature compensation, and can be aligned without mechanically adjusting inductors and/or capacitors in the tuned circuits.

Method and apparatus for tuning and aligning an FM receiver

An enhancement implant used in late programming of a ROM in an integrated circuit is combined with a depletion implant used much earlier in the fabrication process to also permit late programming of power paths in the integrated circuit. The implants must be matched and the IC heated after the enhancement implant.

Stephen L. Inman

Papers

Phase locked loop circuit with digital control

Method and apparatus for tuning and aligning an FM receiver

Programming power paths in an IC by combined depletion and enhancement implants