An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

This invention clarifies the effects of parameters and enables the mass production of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. The quantity of impurities in n drift regions is within the range between 100% and 150% or between 110% and 150% of the quantity of impurities in p partition regions. The impurity density of either one of the n drift regions and the p partition regions is within the range between 92% and 108% of the impurity density of the other regions. In addition, the width of either one of the n drift regions and the p partition regions is within the range between 94% and 106% of the width of the other regions.

Semiconductor device with alternating conductivity type layer and method of manufacturing the same

An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions. The integrated circuit comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower doping level than the substrate; (c) a plurality of body regions of a second conductivity type within the epitaxial layer in the transistor regions; (d) a plurality of trenches within the epitaxial layer in both the transistor regions and the rectifier regions; (e) a first insulating layer that lines the trenches; (f) a polysilicon conductor within the trenches and overlying the first insulating layer; (g) a plurality of source regions of the first conductivity type within the body regions at a location adjacent to the trenches; (h) a second insulating layer over the doped polysilicon layer in the transistor regions; and (i) an electrode layer over both the transistor regions and the rectifier regions.

Trench DMOS transistor with embedded trench schottky rectifier

Improved approaches to providing thermal and power management for a computing device are disclosed. These approaches facilitate intelligent control of a processor's clock frequency and/or a fan's speed so as to provide thermal and/or power management for the computing device.

Thermal and power management for computer systems

A semiconductor device (10) having a termination structure (25) and a reduced on-resistance. The termination structure (25) is fabricated using the same processing steps that were used for manufacturing an active device region (21). The termination structure (25) and the active device region (21) are formed by etching trenches (22, 23) into a drift layer (14). The trenches (22, 23) are filled with a doped polysilicon trench fill material (24), which is subsequently planarized. The semiconductor device (10) is formed in the trenches (22) filled with the polysilicon trench fill material (24) that are in the active region. The trenches (23) filled with the polysilicon trench fill material (24) in a termination region serve as termination structures.

Semiconductor device and method of manufacture

A method for fabricating a dual gate thin film transistor using a power MOSFET process having a first gate area (22) made from a monocrystalline silicon. A dielectric layer (25) is formed over the monocrystalline silicon. A first gate electrode (58) contacts the first gate area (22). A thin film transistor is fabricated on a first island of polysilicon (29) over the dielectric layer (25). The thin film transistor has a second gate electrode (55), and drain and source electrodes (56, 57) wherein the drain and source electrodes (56, 57) contact different portions of the first island of polysilicon (29). Preferably, the first gate electrode (58) is coupled to the second gate electrode (55).

Fabricating dual gate thin film transistors

FET protection circuit (10; 100) senses the temperature of a FET (11) and, via a control circuit (24), increases FET conduction in response to sensed FET temperature exceeding a high temperature threshold (160° C.) close to the maximum rated junction temperature (175° C.) of the FET. This allows the FET to survive excessive drain-to-source voltages which occur during load dump conditions even when load dump is sensed by a zener diode (26) which initially turns on the FET. During load dump after a zener diode (26) turns on the FET, in response to sensing excessive FET temperature the FET is turned in harder so as to reduce the drain-to-source voltage (V DS ) and minimize power dissipation during load dump thereby protecting the FET. Normal overcurrent and maximum temperture turn off circuitry (44, 33, 60-63) is effectively overridden by high temperature threshold turn-on circuitry (50). Preferably, a majority of the control circuit (24) is provided on an integrated circuit, but an external resistor (31) allows effective adjustment of two temperature thresholds (150° C., 160° C.) above which control signals provided to the FET will be modified.

Semiconductor device protection circuit

A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes 28 and 71 between the drain 22 and the gate 20 of the semiconductor device. The diodes 28 protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes 28 and 71 are formed back-to-back in polysilicon 65. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.

Semiconducteur device having high energy sustaining capability and a temperature compensated sustaining voltage

An integrated circuit having a microprocessor core interfaced to large power transistors is described. This integrated circuit provides the capability to intelligently control and drive loads requiring currents exceeding 250 milli amps. The large power transistors are built in a technology compatible with the microprocessor core technology resulting in a more readily manufacturable circuit. The microprocessor core is layed out in a manner which provides the greatest distance between the most heat sensitive microprocessor core circuits and the power devices. On chip temperature sensing and feedback is provided for junction temperature monitoring and control.

Stephen P. Robb

Papers

Semiconductor device and method of manufacture

Fabricating dual gate thin film transistors

Semiconductor device protection circuit

Semiconducteur device having high energy sustaining capability and a temperature compensated sustaining voltage

Microprocessor having high current drive and feedback for temperature control