An electronic system (100) includes a register (TONTOFF) for data and a clock circuit (2340, 708) coupled to the register and responsive to the data in the register to generate a series of clock pulses (CPU-- CLK). The series of clock pulses occupies time intervals (2550) interspersed with time intervals free of clock pulses (2552), as an output having a ratio of the time intervals responsive to the data. Other devices, systems and methods are also disclosed.

Power management masked clock circuitry, systems and methods

A microprocessor device (102) includes a central processing unit (702) having a clock input, a clock generator (OSC, PLL) of clock pulses, a logic circuit (708) having an output to supply a clock control signal (SUSP), and a clock gate (3610) fed by the clock pulses and having a clock gate output (CPU -- CLK) coupled to the clock input of the central processing unit. The clock gate (3610) responds to the clock control signal (SUSP) to prevent said clock pulses (CPU -- CLK) from reaching the central processing unit within one clock cycle of a change in said clock control signal. Other devices, systems and methods are also disclosed.

Clock control circuits, systems and methods

An interrupt request processing device and method for control of the bus cycle of a microprocessor which implements predetermined wait periods dependent upon a detected wait request. Predetermined wait states, programmable in the microprocessor, are assigned to wait request signals for implementation of a predetermined wait period corresponding to a detected wait request signal, in which the bus cycle is suspended for the predetermined wait period while the signal to be applied to the connected peripheral device is held during access to the peripheral device. After the predetermined wait period is over the bus cycle is unsuspended and the microprocessor is again able to detect wait request signals.

Apparatus for suspending the bus cycle of a microprocessor by inserting wait states

A system (100) for computer power management for a computer (102) having a clock (706), includes a plurality of sampling circuits (2360, 2350, 4630, 4720, 4810, 3400, 5300, 5400) responsive to different system activity levels and producing system activity signals representative of the system activity levels. More circuitry (120, 106, 4640) is responsive to the system activity signals and supplies weighted activity output signals adjustably weighting the system activity levels. Filter circuitry (702, 4680) continually responds to the weighted activity output signals to produce a series of duty cycle-related control signals (TONTOFF) representative of directions to pulse-width modulate (MASKCLK) the clock of the computer with such duty cycle. Other devices, systems and methods are also disclosed.

Adaptive power management processes, circuits and systems

A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.

Multiple frequency output clock generator system

A clock control apparatus that stops a system clock in a high performance high speed computer a determined number of system clock cycles after the generation of the clock control signal by a digital computer. The apparatus receives a basic clock signal and the clock control signal and generates a system clock for the system. The system clock includes a normal system clock signal and at least one early system clock signal. The basic clock is provided through a delay tap generating a normal basic clock signal and at least one early basic clock signal. In addition, a control state machine receiving the normal basic clock signal and the at least one early basic clock signal and responsive to the clock control signal is provided for starting and stopping the system clock. The clock control signal is synchronized with the earliest system clock and supplied to the clock control state machine.

Stephen S. C. Si

Papers

Deterministic clock control apparatus for a data processing system