Several different models for predicting coverage in a fault-tolerant system, including models for permanent, intermittent, and transient errors, are discussed. Markov, semi-Markov, nonhomogeneous Markov, and extended stochastic Petri net models for computing coverage are developed. Two types of events that interfere with recovery are examined; and methods for modeling such events, whether they are deterministic or random, are given. The sensitivity of system reliability/availability to the coverage parameter and the sensitivity of the coverage parameter to various error-handling strategies are investigated. It is found that a policy of attempting transient recovery upon detection of an error (as opposed to automatically reconfiguring the affected component out of the system) can actually increase the unreliability of the system. >

Coverage modeling for dependability analysis of fault-tolerant systems

FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single-line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults. >

Extraction and simulation of realistic CMOS faults using inductive fault analysis

This paper presents efficient n-way plurality and threshold voting algorithms based on the type of voting (exact, inexact, or approval), rule for output selection (plurality or threshold) and properties of the input object space (size and structure). Exact voting is the most common voting method and is the easiest to implement. Inexact voting algorithms are more complicated due to intransitivity of approximate equality. In approval voting, each input to the voting process consists of a finite or infinite set of values that have been "approved" by the corresponding computation channel and the value, or set of values, with the highest approval voting must emerge as output. Multiple approved values can result from a nonunique answer to a given problem or from uncertainties in the solution process. For exact voting, the complexity of an n-way voting algorithm depends on the structure of the input object space. Threshold voting often requires less time and space, except when the threshold is very small. The author extends the techniques for designing efficient exact voting algorithms to inexact and approval voting schemes. Results show that optimal linear-time (in n) voting algorithms are available when the input object space is small. Next in the time-complexity hierarchy is the case of a totally-ordered object space that supports worst-case order-[n/spl middot/log(n)]-time algorithms for both exact and inexact voting as well as for certain approval-voting schemes. >

Voting algorithms

FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single-line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults.<<ETX>>

Extraction and Simulation of Realistic CMOS Faults using

It is little more than 15-years since the idea of Iddq testing was first proposed. Many semiconductor companies now consider Iddq testing as an integral part of the overall testing for all IC's. This paper describes the present status of Iddq testing along with the essential items and necessary data related to Iddq testing. As part of the introduction, a historical background and discussion is given on why this test method has drawn attention. A section on physical defects with in-depth discussion and examples is used to illustrate why a test method outside the voltage environment is required. Data with additional information from case studies is used to explain the effectiveness of Iddq testing. In Section IV, design issues, design styles, Iddq test vector generation and simulation methods are discussed. The concern of whether Iddq testing will remain useful in deep submicron technologies is addressed (Section V). The use of Iddq testing for reliability screening is described (Section VI). The current measurement methods for Iddq testing are given (Section VII) followed by comments on the economics of Iddq testing (Section VIII). In Section IX pointers to some recent research are given and finally, concluding remarks are given in Section X.

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Iddq Testing for CMOS VLSI

A New Fault Model and Testing Technique for CMOS Devices.

Reconfiguration schemes for replacing faulty cells (processing elements) with spare cells are introduced for massive parallel rectangular mesh array processors with fine-grained cells. The authors introduce the concept of two-level redundancy as an effective way of using redundant units to reduce the complexity of reconfiguration control circuitry, to limit the length of connecting wires after reconfiguration, and to increase the manufacturing yield and the operation reliability. An optimization technique for allocating the redundant cells into both levels is presented. The operational reliability and manufacturing yield of arrays with two-level redundancy are presented. The yield estimation problem is modeled by an occupancy problem in classical combinatorial analysis. Both distributed and clustered defects are taken into consideration in the yield estimation. >

Reconfiguration of VLSI/WSI mesh array processors with two-level redundancy

Functional testing is becomilng more important due to the increasing complexity in digital LSI/VLSI devices. Various functional testing approaches have been proposed to meet this urgent need in LSI/VLSI testing. This paper presents the basic ideas behind deterministic functional testing and concisely overviews eight major functional testing techniques. Comparisons among these techniques and suggestions for future development are made to meet the challenges in this fast growing testing field.

Functional Testing Techniques for Digital LSI/VLSI Systems

A method is presented for functional testing of microprocessors. First, a control fault model at the RTL (register transfer language) level is developed. Based on this model, the authors establish testing requirements for control faults. They present two test procedures to verify the write and read sequences, and use the write and read sequences to test each instruction in the microprocessor. By utilizing k-out-of-m codes, they use fewer tests to cover more faults, thereby reducing the test generation time. >

Stephen Y. H. Su

Papers

A New Fault Model and Testing Technique for CMOS Devices.

Reconfiguration of VLSI/WSI mesh array processors with two-level redundancy

Functional Testing Techniques for Digital LSI/VLSI Systems

A functional testing method for microprocessors

Testing Functional Faults in Digital Systems Described by Register Transfer Language.