A trace array with added width is provided. Each trace array entry includes a data portion and a side counter portion. When a programmable subset of trace data repeats, a side counter is incremented. When the programmable subset of the trace data stops repeating, the trace data and the side counter value are stored in the trace array. The trace array may also include a larger counter. In this implementation, if the smaller side counter reaches its maximum value, a larger counter may begin counting. The larger counter value may then be stored in its own trace array entry instead of the trace data. A predetermined side counter value may mark the entry as a larger compression counter instead of as a data entry.

Method and apparatus for achieving high cycle/trace compression depth by adding width

A rotary traveling wave oscillator (RTWO) frequency divider design methodology is proposed for dynamic frequency scaling. The proposed methodology can be used for designing dividers for integer division ratios of 3 to 9 within one circuit topology. HSPICE-based experiments are performed to test the electrical characteristics of the RTWO frequency dividers. The simulation results show that the power consumption of a frequency divider is as low as approximately 5mW for different frequency division ratios.

Resonant frequency divider design methodology for dynamic frequency scaling

The shift register, which is an n-th shift register of a shift register chain, includes a first multiplexer, a second multiplexer, and a latch block, wherein n is a positive integer. The first multiplexer selects one of output data of the (n−1)-th shift register or output data of the (n+1)-th shift register and outputs the selected data to be used as a reset signal in the latch block. The second multiplexer selects one of the output data of the (n−1)-th shift register or the output data of the (n+1)-th shift register and outputs the selected data to be used as input data of the latch block. The latch block stores the output data of the second multiplexer in response to the clock control signal, the inverted clock control signal and the reset voltage, and outputs the stored data.

Shift register having low power consumption and method of operation thereof

Some embodiments of the invention includes a data generator. The data generator includes a data generating circuit having a combination of linear feedback shift registers and shift registers for generating a pseudo-random data pattern in a first order. The data generator also includes a recovery circuit for allowing the data generating circuit to generate the pseudo-random data pattern in a second order. The second order is a reverse of the first order. Other embodiments are described and claimed.

Data generator having linear feedback shift registers for generating data pattern in forward and reverse orders

Various clock frequency dividers are disclosed. Each frequency divider includes cascaded flip-flops and a feedback logic gate. First data inputs of the flip-flops are for propagating logic values along the cascaded flip-flops and the feedback gate for generating valid states of a sequence in response to a clock signal. Each frequency divider includes an invalid state elimination circuit configured to detect an invalid state at the outputs of the flip-flops and change it into a valid state in response to the clock signal. In some implementations, the invalid state elimination circuit includes a NOR gate to detect an all-zero invalid state and generate a control signal to cause the flip-flops to output logic values associated with a valid state or to cause a multiplexer to introduce a logic value associated with a valid state. In other implementations, the invalid state elimination circuit instead includes an AND gate to detect an all-ones invalid state.

Apparatus and method for clock signal frequency division using self-resetting, low power, linear feedback shift register (LFSR)

An apparatus and method for providing a high speed linear feedback shift register is disclosed. The high speed linear feedback shift register of the present invention comprises multiplexer flip flop circuits. The multiplexer gate on the input of each flip flop circuit is the only gate between each pair of flip flop circuits of the present invention. The linear feedback shift register of the present invention is capable of operating as a counter that does not need to be reset. The linear feedback shift register of the present invention may be used as a clock divider circuit.

Steve Kommrusch

Papers

High speed linear feedback shift register