Continuous advances in VLSI technology have made it possible to implement a system on a chip. One consequence of this is that the system will use a homogeneous technology for interconnections, gates, and synchronizers. Another consequence is that the system size and operation speed increase, which leads to increased problems with timing and synchronization. System and delay models necessary for the study of time performances of synchronous and asynchronous systems are developed. Clock skew is recognized as a key factor for the performance of synchronous systems. A mode of clocking that reduces the clock skew substantially is proposed and examined. Time penalty introduced by synchronizers is recognized as a key factor for the performance of asynchronous systems. This parameter is expressed in terms of system parameters. Different techniques and recommendations concerning performance improvement of synchronous and asynchronous systems are discussed. >

Performance of synchronous and asynchronous schemes for VLSI systems

We explore the practical limits on throughput imposed by timing in a long, self-timed, circulating pipeline (ring). We consider models with both fixed and random delays and derive exact results for pipelines where these delays are fixed or exponentially distributed random variables. We also give relationships that provide upper and lower bounds on throughput for any pipeline where the delays are independent random variables. In each of these cases, we show that the asymptotic processor utilization is independent of the length of the pipeline; thus, linear speedup is achieved. We present conditions under which this utilization approaches 100%.

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Bubbles can make self-timed pipelines fast

Clock distribution networks synchronize the flow of data signals between data paths, and the design of these networks can dramatically affect system wide performance and reliability. The field of clock distribution design can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom VLSI systems; 2) the automated synthesis of clock distribution networks with application to automated synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells, and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the specification of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described and summarized. Future trends are discussed. >

Clock distribution design in VLSI circuits-An overview

This dissertation presents a novel technique for high-bandwidth communication called STARI, Self-Timed At Receiver's Input. STARI is a hybrid of synchronous and self-timed design techniques. STARI is provably correct, well suited for CMOS implementation, and offers a practical, cost effective approach to interprocessor communication in a multiprocessor. To demonstrate STARI, a CMOS chip has been implemented and is described here.
STARI is motivated by limitations of purely synchronous or purely self-timed hardware. This dissertation begins with an asymptotic analysis of the performance of self-timed pipelines. It is shown that self-timed pipelines can achieve linear speedup under an assumption of uniform interconnect delays. However, practical designs have non-uniform interconnect because of the hierarchy of packaging. In these designs, the performance is limited by the latency of the slowest interconnect.
To exploit the high-bandwidth offered by STARI in a multiprocessor, each processor node must have a memory system that offers high-bandwidth data transfers to the STARI interface and low latency access to the local CPU. Dual-port memories allow both of these goals to be met. Consistency problems that arise when using dual-port memories are identified and two software solutions are presented and analyzed.

Stari: a technique for high-bandwidth communication

In-vitro methods for protein structure determination are time-consuming, cost-intensive, and failure-prone. Because of these expenses, alternative computer-based predictive methods have emerged. Predicting a protein’s 3-D structure from only its amino acid sequence—also known as ab initio protein structure prediction (PSP)—is computationally demanding because the search space is astronomically large and energy models are extremely complex. Some successes have been achieved in predictive methods but these are limited to small sized proteins (around 100 amino acids); thus, developing efficient algorithms, reducing the search space, and designing effective search guidance heuristics are necessary to study large sized proteins. An on-lattice model can be a better ground for rapidly developing and measuring the performance of a new algorithm, and hence we consider this model for larger proteins (>150 amino acids) to enhance the genetic algorithms (GAs) framework. In this paper, we formulate PSP as a combinatorial optimization problem that uses 3-D face-centered-cubic lattice coordinates to reduce the search space and hydrophobic-polar energy model to guide the search. The whole optimization process is controlled by an enhanced GA framework with four enhanced features: 1) an exhaustive generation approach to diversify the search; 2) a novel hydrophobic core-directed macro-mutation operator to intensify the search; 3) a per-generation duplication elimination strategy to prevent early convergence; and 4) a random-walk technique to recover from stagnation. On a set of standard benchmark proteins, our algorithm significantly outperforms state-of-the-art algorithms. We also experimentally show that our algorithm is robust enough to produce very similar results regardless of different parameter settings.

An Enhanced Genetic Algorithm for Ab Initio Protein Structure Prediction

A probabilistic model for the accumulation of clock skew in synchronous systems is presented. The model is used to derive upper bounds for expected skew and its variance, in tree distribution systems with N synchronously clocked processing elements. The results are applied to two specific models for clock distribution. In the first, which is called metric-free, the skew in a buffer stage is Gaussian with a variance independent of wire length. The second, metric, model, is intended to reflect VLSI constraints: the clock skew in a stage is Gaussian with a variance proportional to wire length, and the distribution tree is an H-tree embedded in the plane. Upper bounds on skew are obtained for both models. Estimates of the constants of proportionality as well as the asymptotic behavior have been obtained and verified by simulation. >

A probabilistic model for clock skew

A scalable architecture for lattice-gas simulations

Performance of VLSI Engines for Lattice Computations.

We address t he problem of designin g an d building efficient custo m Vl.Sl-besed processors to do computat ions on large multi -dimensional lat tices. The design t ra deoffs for two architectures which provid e practical engines for lattice updates are deri ved and an alyzed . We find t hat I/O constit utes t he principal bottleneck of processors des igned for lat t ice computations, and we derive upp er bounds on t hroughp ut for lattice updates based on Hong and Kung's graph-pebbling argument t ha t model s I/ O. In part icular, we show that R = O(BS1/ d ) , where R is the site update rate, B is t he main memory bandwidth, S is t he processor sto rage, and d is t he dimension of th e la ttice.

Steven D. Kugelmass

Papers

A probabilistic model for clock skew

A scalable architecture for lattice-gas simulations

Performance of VLSI Engines for Lattice Computations.

Performance of VLSI Engines for Lattice Computations.