A number of local sequencers, one for each pin of the device under test is disclosed Each local sequencer is provided with a global clock, a global time zero signal indicating the clock edge for referencing the start of a test, and a period vernier indicating an offset from the clock for the start of the test period Each local sequencer uses this information to generate its own test events referenced to the test period with individual calibration delays factored in locally Each local sequencer is individually programmable so that different sequencers can provide different numbers of events during the same test period

Event sequencer for automatic test equipment

A microcomputer (10) with external bus interface (15) for providing communication with external peripheral devices such as memory and the like is provided with on-board chip select logic (20, 21, 22, 23, 24) and programmable bus stretching capability (16, 22). The chip select logic provides chip select signals to external devices when addresses fall within pre-selected ranges, eliminating the ''glue'' logic normally required for this purpose. The programmable bus stretching feature inserts a pre-selected number of ''wait states'' into any external bus cycle for which it is programmed by stretching, or freezing, the central processing unit and external bus interface unit clocks. Other internal clocks, such as those which drive timers and/or serial interface baud rate generators are not frozen by the bus stretch.

Microcomputer with on-board chip selects and programmable bus stretching

A reduced instruction set computer processor, having a rapid access, dual port register file for supplying operands to a high speed arithmetic logic unit, is implemented as a set of integrated circuits interconnected by constant impedance transmission lines and synchronized by a common clock signal. The transmission lines interconnecting the integrated circuits are formed by thin metallic foil conductors separated by dielectric polyimide membranes. The clock signal is adjustably delayed prior to transmission to each integrated circuit so that pulses of the clock signal arrive at each integrated circuit at the same time regardless of differences in inherent delays of the separate paths the clock signal must follow to each integrated circuit.

Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits

A clock frequency multiplication circuit. A circuit is described for receiving a clock signal of a first frequency X and multiplying the frequency of the signal by a multiple N to produce a signal of frequency N times X. The circuit is particularly useful in, for example, computer systems in which it is desired to upgrade certain components such as a processor to operate at an increased clock speed without modifying the clock speed of the system clock and where it is further desired to provide synchronization between the system clock and the processor clock.

Clock generator for a computer system

A plurality of "pin slice" circuits, each associated with a separate pin of the device under test (DUT). Each pin slice circuit contains its own memory and registers and circuitry for generating the necessary test signals. Test data is loaded into the individual pin slice circuits in a vertical word fashion, such that all of the bits of the vertical word correspond to the individual pin, allowing the characteristics of an individual pin test sequence to be varied independently of the other pins. A participate memory is used to select different groupings of the pin slice circuits which are to be programmed in parallel when a group of pins are to receive the same test signals. Separate enable signals to the various stages of the pin slice circuits allow different aspects of the test pattern to be also varied independently.

Automatic test equipment system using pin slice architecture

The present apparatus includes logic for stopping timing circuits in a central processing unit and for restarting the timing circuits to produce timing signals synchronized with an asynchronous external signal. The continuous running master clock of the central processing unit is employed to generate a plurality of phase related new clock signals. Logic circuit means are provided to sequentially attempt to employ each of the new clock signals until one of the new clock signals synchronizes with the external asynchronous signal. The logic circuit means include circuits for selecting a new clock signal to be employed by the timing circuits of the central processing unit so that the new clock is synchronized with the external asynchronous signal.

Steven M. O'Brien

Papers

High speed processing restarting apparatus