An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A low profile multi-IC chip package for high speed application comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with buses formed on one side. In another embodiment, the connector comprises multiple buses formed from conductive polymer. In further embodiments, the primary packages are stacked within a cage and have their outer leads in unattached contact with buses within the cage or, alternatively, are directly fixed to leads or pads on the host circuit board.

Low profile multi-IC chip package connector

The present invention relates to an improved method for forming a UBM pad and solder bump connection for a flip-chip which eliminates at least two mask steps required in standard UBM pad forming processes when repatterning the bond pad locations.

Mask repattern process

The present invention relates to an improved method for forming a UBM pads and solder bump connections for flip chip which eliminates at least one mask step required in standard UBM pad forming processes. The method also includes repatterning bond pad locations.

Method of forming conductive bumps on die for flip chip applications

An integrated circuit (50) has a wire bond pad (53). The wire bond pad (53) is formed on a passivation layer (18) over active circuitry (26) and/or electrical interconnect layers (24) of the integrated circuit (50). The wire bond pad (53) is connected to a plurality of final metal layer portions (51, 52). The plurality of final metal layer portions (51, 52) are formed in a final interconnect layer of the interconnect layers (24). In one embodiment, the bond pad (53) is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad (53) allows routing of conductors in a final metal layer (28) directly underlying the bond pad (53), thus allowing the surface area of the semiconductor die to be reduced.

Semiconductor device having a wire bond pad and method therefor

A semiconductor device (32) has an as-deposited solder bump (34) having the intrinsic potential for forming an extended eutectic region for simplified DCA applications. The as-deposited solder bump (34) has first tin layer (40) overlying the UBM of the bonding pad (14) on the device. The first tin layer reacts with a metal layer (36) in the UBM to form an intermetallic for adhering the solder bump to the bonding pad. A thick lead layer (42) overlies the first tin layer to provide the substantial component of the solder bump. A second tin layer (44) overlies the lead layer to provide localized eutectic formation at the top surface of the bump during reflow. A device having at least this solder bump structure can be directly attached to either ceramic or PC board substrates. Additional layers of tin and /or lead may be supplemented to the basic bump structure to optimize the eutectic formation rate.

Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same

A nodular metal paste (42) is used to temporarily attach the bumps (34) on a semiconductor die (32) to a substrate (38). The spherical nodules (44) composing the metal paste are dispensed onto contact pads (40) on the substrate, and then heated until they partially melt. The partial liquid region permits bonding of the individual metal nodules to the contact pads and to adjacent nodules. Subsequently, a bumped die is placed over the nodules and heated to a minimum temperature required to partially remelt to form a local tack joint. Because the metallurgical contact area between the paste nodules and the bumps is minimized, electrical contact can be sustained with a small cross-sectional area of connected material to create an electrically sound but physically weak link between die and the substrate. Once connected to the substrate, the die may be tested and burned-in, and removed afterwards with little damage to the bumps.

Method for forming a temporary attachment between a semiconductor die and a substrate using a metal paste comprising spherical modules

A mostly copper-containing interconnect ( 126 ) overlies a semiconductor device substrate ( 100 ), and a transitional metallurgy structure ( 312, 508, 716, 806 ) that includes an aluminum-containing film ( 200, 506, 702, 802 ) contacts a portion of the mostly copper-containing interconnect. In one embodiment, the transitional metallurgy is formed over a portion of a bond pad ( 128 ). In an alternative embodiment, the transitional metallurgy includes an energy alterable fuse portion ( 710 ) that electrically contacts two conductive regions ( 712 and 714 ), and in yet another embodiment, the transitional metallurgy is formed over a copper-containing edge seal portion ( 809 ).

Method of forming copper interconnection utilizing aluminum capping film

In accordance with one embodiment of the present invention, a semiconductor device underbump metallurgy ( 414 ) is formed over a semiconductor bond pad ( 128 ), wherein the underbump metallurgy ( 414 ) comprises a chromium, copper, and nickel phased-region ( 404 ), and wherein the presence of nickel in the phased-region ( 404 ) inhibits conversion of tin from the solder bump and other tin sources from forming spallable Cu 6 Sn 5 copper-tin intermetallics.

Semiconductor device and method of formation

Flip-chip is fast becoming the mounting method of choice in the semiconductor industry for dice having a high number of contacts. Since many applications require known-good-die, these flip-chip semiconductor dice must be tested and burned-in. By testing and burning-in the semiconductor wafers prior to solder bumping, the probe tips (42, 44, 46 & 48) can contact the hard planar surface of the under-bump-metallurgy (40) on each bonding pad (14) for easier and more reliable contact and hence test results. The probe tips can be either of an array (42 & 44) or cantilevered needle (46 & 48) type. Blunt probe tips (42 & 48) are well-suited to making contact on the shoulder of each bonding pad of each semiconductor die, while sharp probe tips (44 & 46) are preferable for contacting the center of each bonding pad. Solder bumping is performed post-testing.

Stuart E. Greer

Papers

Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same

Method for forming a temporary attachment between a semiconductor die and a substrate using a metal paste comprising spherical modules

Method of forming copper interconnection utilizing aluminum capping film

Semiconductor device and method of formation

Method for testing and burning-in a semiconductor wafer