This paper presents a continuous-time (CT) multi-stage noise-shaping (MASH) ADC in 28 nm CMOS. The MASH ADC uses a first-order front-end stage to digitize the input signal and a second-order back-end stage to digitize the quantization noise of the coarse flash ADC inside the front-end. An RC lattice filter and a current-steering DAC are utilized to extract the front-end coarse quantization residue. The prototype MASH ADC chip built in a 28 nm CMOS process is clocked at 8 GHz with an OSR of 8.6, providing a signal bandwidth of 465 MHz. The ADC achieves a DR of 72 dB and an average small-signal NSD of −160 dBFS/Hz. The peak SNR is 68 dB and the peak SNDR is 67 dB. The IM3 is −88 dBFS with two −9 dBFS tones at the band edge. The ADC consumes 890 mW of power from +1.8/1.0/-1.0 V supplies and achieves a thermal noise FOM of 159 dB.

A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS

An oversampled continuous-time (CT) pipeline ADC clocked at 9 GHz achieving 1.125-GHz bandwidth and −164 dBFS/Hz average small-signal noise density is presented. In contrast to traditional discrete-time (DT) pipeline ADCs, the system processes the signals in CT form throughout all the pipeline stages and thus sampling-induced artifacts such as aliasing and high-peak ADC driving current are mitigated. Despite the oversampled nature of the ADC, its digitization bandwidth is on par with that of traditional non-interleaved DT pipeline ADCs since CT signal processing is not constrained by settling time requirements. The ADC was fabricated in a 28-nm CMOS process technology and consumes 2.3 W.

A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving −164-dBFS/Hz NSD

High-BW continuous-time ΔΣ modulators (CTDSMs), which directly inject excess loop delay compensation (ELDC) at the quantizer input, suffer from the over-range issue due to the 1+αz−1 transfer function of the local feedback loop, where α is the zero-order path coefficient [1–2]. For example, the swing or number of quantization levels will be doubled if α=1 is chosen. On the other hand, injecting the compensation current at the input of the last integrator requires an additional DAC and extra power to minimize excess phase shift [3]. The phase-feedback VCO-based integrating quantizer (VCOIQ) in [4] suggests a unique feature to compensate ELD in the phase domain. In this work, the VCO outputs are rotated directly in the digital domain to implement phase-domain ELDC (PD-ELDC) [5] without overloading any previous stages. Though VCOIQ is essentially a time-domain flash quantizer with a potentially higher number of quantization levels than voltage-domain counterparts, prior work utilized 5b or less when embedded within a CTDSM. The requirement of the low-complexity thermometric DAC limits the maximum number of bits that can be used to fulfill the SQNR specification. In this work, rotating splitters (RSPT) and a segmented DAC are used to increase the VCOIQ resolution to 7b. This arrangement decouples VCOIQ optimization from DAC design constraints and fully exploits the advantage of time-domain quantization. By leveraging the techniques mentioned above, this CTDSM achieves 125MHz BW while operating at 2.15GHz. The measured SNDR/DR are 71.9dB/74.8dB at the input frequency of 1/3 BW.

28.3 A 125MHz-BW 71.9dB-SNDR VCO-based CT ΔΣ ADC with segmented phase-domain ELD compensation in 16nm CMOS

This paper proposes a multistage noise-shaping continuous-time sigma-delta modulator (CT $\Sigma \Delta \text{M}$ ) with on-chip RC time constant calibration circuits, multiple feedforward interstage paths, and a fully integrated noise-cancellation filter (NCF). The core modulator architecture is a cascade of two single-loop second-order CT $\Sigma \Delta \text{M}$ stages, each of which consists of an integrator-based active- RC loop filter, current-steering feedback digital-to-analog converters, and a 4-b flash quantizer. On-chip RC time constant calibration circuits and high-gain multistage operational amplifiers are realized to mitigate quantization noise leakage due to process variation. Multiple feedforward interstage paths are introduced to: 1) synthesize a fourth-order noise transfer function with dc zeros; 2) simplify the design of NCF; and 3) reduce signal swings at the second-stage integrator outputs. Fully integrated in 40-nm CMOS, the prototype chip achieves 74.4 dB of signal-to-noise-and-distortion ratio (SNDR), 75.8 dB of signal-to-noise ratio, and 76.8 dB of dynamic range in 50.3 MHz of bandwidth (BW) at 1 GHz of sampling frequency with 43 mW of power consumption (P) from 1.1/1.15/2.5-V power supplies. It does not require external software calibration and possesses minimal out-of-band signal transfer function peaking. The figure-of-merit (FOM), defined as $\text {FOM}=\text {SNDR}+10\times \log _{10}(\text {BW}/\text {P})$ , is 165.1 dB.

A 43-mW MASH 2-2 CT $\Sigma \Delta$ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS

The world has been in combat with COVID-19 since December 2019. The United States has been paralyzed, with the highest number of cases and more deaths than any other country. However, the disease has devastated almost every nation across the globe, from the Far East to Europe, Latin America, Russia, and India.

/pdf/emerging-blood-gas-monitors-how-they-can-help-with-covid-19-310ugnf4tn.pdf

Emerging Blood Gas Monitors: How They Can Help With COVID-19

Continuous-time delta-sigma modulators (CT-DSMs) are well suited for the baseband ADC of an LTE-A receiver. To boost user throughput and increase network capacity, CT-DSMs will need to increase signal bandwidth (BW) while maintaining sufficient dynamic range (DR) and good power efficiency. For example, 5 downlink component carriers are no longer sufficient to meet the ITU requirement for IMT-advanced and up to 32 carriers and 640MHz RF bandwidth are under discussion for 3GPP Release 13. This increased BW drives CT-DSMs to operate at a several-GHz clock rate, but comes at a cost of higher power consumption, even when utilizing advanced nanometer CMOS technologies. Previous >100MHz-BW CT-DSMs required a 4GHz clock rate with oversampling-ratio (OSR) beyond 13× and power exceeding 250mW [1,2]. By contrast, the proposed CT-DSM decreases the OSR to 9× while consuming 40mW to achieve 72dB DR within 160MHz BW.

15.6 A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique

Recently, biosensors have become widely deployed in consumer wearable devices, e.g., smart watches and wrist bands, to track user health conditions during sport, sleep, and daily activity. However, unlike biosignal acquisition in well-controlled medical settings, signal acquisition in consumer devices inevitably suffers from degraded signal quality due to poor sensor interfaces, motion artifacts, and environmental interferences, such as ambient light and power-line coupling, which can be >60dB stronger than the wanted signals. These challenges result in demanding AFE specifications, even under tight constraints on sensor area, chip size, and battery capacity, which are all necessary for wearable devices. This paper presents a multimodal biosensing SoC that addresses these issues to enable reliable Photoplethysmography (PPG), Electrocardiography (ECG), and Bio-impedance (BIOZ) acquisition under highly variable conditions in wearable devices. It contains a 130dB-DR PPG readout, which is 11dB higher than the state of the art [1], to tolerate strong ambient light; an ECG AFE with a pseudo Right-Leg-Drive (RLD) tolerant of >130V PP common-mode interference (CMI) from power-line coupling, which is 3× higher than the technique presented in [2]; and a BIOZ AFE for body-fat measurement using 1cm2 electrodes rather than the typically >10cm2 electrodes in conventional body-fat meters. The area for the entire PPG/ECG/BIOZ AFE is ~3mm2, which is around 50% smaller than prior AFEs with similar features [3], [4].

26.1 A 4.5mm 2 Multimodal Biosensing SoC for PPG, ECG, BIOZ and GSR Acquisition in Consumer Wearable Devices

High-precision current-measurement front-ends are widely used in various applications, such as photoplethysmography (PPG) recording by biomedical sensors and molecular-concentration detection by electrochemical sensors. They usually require a low noise level down to pA to monitor small signal variations and a wide input range over µA to avoid saturation caused by large input fluctuations. The low-noise-level and wide-input-range requirements typically result in a dynamic range (DR) greater than 120dB. Prior high-DR current measurement front-ends either operate in the time domain using a capacitive-feedback TIA to integrate the input current and then digitize the output voltage via a digital counter [1], or operate in the frequency domain using an Hourglass ADC [2] or asynchronous DFFs [3]. Such methods can reduce the noise level by extending the integration time but suffer from a low conversion frequency (F conv ) as a result. To extend the input range, DC cancellation servo loops [1] or predictive DACs [2] are adopted, but the limited loop bandwidth results in a slow settling or saturation when the signal experiences a rapid change. Utilizing these methods, the previous works achieved an effective DR of ~120dB at F conv of 300-500Hz. This work adopts a different approach of simply increasing the DR of a continuous-time (CT) incremental ADC (IADC) to 140dB without any of the aforementioned methods and achieve a high F conv of 4 kHz. While the noise level and input range of the current-input CT-IADC are both determined by the feedback DAC within the modulator loop, this high DR is realized by increasing the number of DAC MSBs to extend the input range and disconnecting the inactive DAC cells to remove their noise contribution. The noise level is further minimized by adding extra LSB bits so that only the small LSB cells are active when the input approaches 0. In this work, an 11b resistive DAC (RDAC) together with a 12b SAR quantizer are implemented to achieve an input range of 200µA. Meanwhile, a tri-level {−1, 0, +1} DAC with reset-then-open (RTO) operation is introduced to disconnect the MSB cells dynamically without the issue of inter-symbol interference (ISI). To linearize the 11b DAC, a hybrid mismatch error shaping (HMES) scheme which combines segmented noise-shaped scrambling (SNSS) [4] and mismatch error shaping (MES) [5] is presented. This IADC with on-chip voltage references consumes 1.011mW from 1.2V and achieves >200dB FoM with an integral non-linearity (INL) of 8ppm.

9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s

This work presents a continuous-time delta-sigma modulator (CTDSM) using a time-interleaved noise-shaping quantizer targeted for wireless communication system application. A quantization error duplication method enables the SAR-based quantizer to implement noise-shaping and operate at an 832MHz sampling frequency concurrently. Through the use of a CRFB loop filter topology and the noise-shaping quantizer, the proposed CTDSM achieves 71.4 dB SNDR in 30-MHz BW without STF peaking. The FoMs and FoMw are 171 dB and 17.6 fJ/conv.-step, respectively.

A 71. 4dB SNDR 30MHz BW Continuous-Time Delta-sigma Modulator Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm CMOS

This work presents a time-multiplexing SAR ADC to support up to 5-lead ECG monitoring with >100dB SNDR per readout channel. Its noise and linearity performance are enhanced by a combination of dual-reference architecture and mismatch error shaping (MES) technique without using amplifiers or calibration, resulting in >106dB SFDR and 109.4dB DR within 250Hz bandwidth (FoM S,DR =178.9dB). The ECG analog front-end (AFE), including 3 DC-coupled instrumentation amplifiers (IAs) and 1 ADC, occupies only 0.48mm2 in 55nm CMOS. Each ECG channel achieves 1μV rms (0.5-250Hz) input-referred noise at a low IA gain of 6V/V with a 667mV pp-diff linear input range.

Su-Hao Wu

Papers

15.6 A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique

26.1 A 4.5mm 2 Multimodal Biosensing SoC for PPG, ECG, BIOZ and GSR Acquisition in Consumer Wearable Devices

9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s

A 71. 4dB SNDR 30MHz BW Continuous-Time Delta-sigma Modulator Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm CMOS

An Amplifier-Less Calibration-Free SAR ADC Achieving >100dB SNDR for Multi-Channel ECG Acquisition with 667mV pp Linear Input Range