A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.

Architectural Floorplan for a Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node or Smaller

Certain exemplary embodiments can provide a system, machine, device, manufacture, circuit, and/or user interface adapted for, and/or a method and/or machine-readable medium comprising machine-implementable instructions for, activities that can comprise, based on a predicted non-zero future power requirement for performing one or more portions of an expected workload by a predetermined system, the predicted future power requirement based on a past power requirement for performing one or more portions of a known workload by the predetermined system, automatically causing a change from a first power state of the predetermined system to a second power state that does not violate a specification for performing the one or more portions of the expected workload.

Systems, devices, and/or methods for managing energy usage

Power supply voltage to an integrated circuit (IC) or a portion of an IC is maintained at an optimum level matching the IC performance. Voltage ranges and delay measures for corresponding operating frequencies are stored in tables in a voltage control block. When a new frequency of operation is desired, the voltage control block measures delay performance of the IC, and sets the supply voltage to a value specified in a corresponding entry in a table. The voltage control block then continues to measure delay performance, and dynamically adjusts the power supply voltage to an optimum value thereby minimizing power consumption.

Maintaining Optimum Voltage Supply To Match Performance Of An Integrated Circuit

The present invention addresses the problem of a second (or higher) order representation of a transmit signal which is transmitted by a transceiver being mixed into the region of the frequency spectrum of interest to the transceiver receiver, such that it can not then be spectrally filtered out. At its most straightforward, in one embodiment of the invention this is achieved by providing a cross-talk cancellation unit which takes the transmit signal, and obtains the second (or higher) order representation thereof. This representation is then subtracted from the received signal before the signal is passed to the radio control receiver signal processing elements. However, in a more preferred arrangement a filter is also provided, to filter the second or higher order version of the transmit signal, prior to its being subtracted from the received signal. The filter basically takes out the effects of any other filtering or processing which has happened to the transmit signal in the receiver signal chain. This would be, for example, the filtering effects provided by the anti-aliasing filter in the receiver.

Method and apparatus for cross-talk cancellation

An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.

Closed loop temperature controlled circuit to improve device stability

A circuit for controlling temperature of a semiconductor chip includes a first heating element that is built into the semiconductor chip. The first heating element generates heat to increase the temperature of the semiconductor chip. The chip also includes a temperature controller that is coupled to the first heating element and built into the semiconductor chip. The temperature controller controls the temperature to enable testing of the semiconductor chip at a desired temperature.

Circuit for controlling temperature and enabling testing of a semiconductor chip

A characteristic is measured on multiple portions of an integrated circuit, and the supply voltage adjusted based on the measurements. In an embodiment, the characteristic corresponds to propagation delay which indicates whether the integrated circuit is implemented with a strong, weak or nominal process corner. In general, the supply voltage can be increased in the case of a weak process corner and decreased in the case of a strong process corner.

Providing optimal supply voltage to integrated circuits

An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.

Current sensing and control for a transistor power switch

Ensuring sufficient bias current is provided to a portion of a circuit containing low voltage transistors operating with a high supply voltage. Such a sufficient bias current may be ensured by generating a primary bias current from a low supply voltage and a backup bias current from a high supply voltage, and providing the backup bias current as the bias current if the primary bias current is not present. The primary bias current may be provided as the bias current when the low supply voltage is available. Thus, the backup bias current is provided as bias current in case of undesirable supply sequencing.

Avoiding excessive cross-terminal voltages of low voltage transistors due to undesirable supply-sequencing in environments with higher supply voltages

A highly-integrated DSL modem for residential gateway applications is described. The chip integrates a C62x based DSL PHY, AFE, line driver and receiver, power management, and broadband controller subsystem. A 0.13/spl mu/m 5M CMOS process is used to implement the 2.3W chip. Supplies are 1.5V for digital and 3.3V for analog subsystems.

https://ieeexplore.ieee.org/iel5/9264/29428/01332732.pdf

Sudheer Prasad

Papers

Circuit for controlling temperature and enabling testing of a semiconductor chip

Providing optimal supply voltage to integrated circuits

Current sensing and control for a transistor power switch

Avoiding excessive cross-terminal voltages of low voltage transistors due to undesirable supply-sequencing in environments with higher supply voltages

A DSL customer-premise equipment modem SoC with extended reach/rate for broadband bridging and routing