Reversible logic is also called information lossless logic, since the information embedded in the circuits can be recovered, if lost. Research carried out by Landauer and Bennett proved that the energy dissipation would not occur if computation is made reversible. With this aim a number of reversible gates were designed and invented. As examples like- the Fredkin gate, the Toffoli gate, the Peres gate, and the Feynman gate. Reversible logic has extensive applications and is considered as one of the futuristic technologies. But the logic circuit designing is based on logic gates, which are non-reversible. This paper presents design of logic gates using reversible gates. These logic gates help in future implementation of higher end circuits. In this paper an attempt is made to design logic gates using reversible gates and some of the higher end circuits are also designed such as Binary-to-Grey, grey-to-Binary, Adder, Subtractor etc. 

Design of Logic Gates using Reversible Gates with Reduced Quantum Cost

Arithmetic and Logical Unit (ALU) is one of the key aspects of the digital world. In generally, it requires a colossal amount of power. This paper outlines a new design of one-bit Parity Preserving Reversible ALU circuit. To design the ALU with low power dissipation, we have used the concept of Reversible Logic computation. Conventional Circuits dissipate an enormous amount of power due to the loss of information bits in computation, but Reversible Circuits has no data loss as one on one mapping between outputs and inputs which leads to the minimization of power dissipation. In our design, we have used Parity Preserving Reversible Gates which are having Fault tolerance property as fault occurring at internal nodes results in an error at the output. So, Parity Preserving Reversible Gates is the one in which Output Parity remains same as of the Inputs. The aimed ALU has been carried out using Xilinx ISE 14.7 version software in Verilog HDL. To demonstrate the efficiency of proposed Parity Preserving Reversible Arithmetic and Logical Unit, each subpart is shown in terms of various parameters such as Quantum cost, Ancilla Inputs, Gate Count and Garbage Outputs and also a comparison with existing work is shown. The intended design is far better than the existing one because of its fault-tolerant capabilities. The proposed ALU extends its application over DNA mapping, Optical computation, cryptography, nanotechnology, quantum computing and digital signal processing.

Design of Parity Preserving Arithmetic and Logic Unit using Reversible Logic Gates

This paper presents a fault-tolerant ALU (“FT-EALU”) based on time redundancy and reward/punishment-based learning approaches for real-time embedded systems that face limitations in hardware and power consumption budgets. In this method, operations are diversified to three versions in order to correct permanent faults along with the transient ones. The diversities of versions considered in FT-EALU are provided by lightweight modifications to differentiate them and clear the effect of permanent faults. Selecting lightweight modifications such as shift and swap would avoid high timing overhead in computation while providing significant differences which are necessary for fault detection. Next, the replicated versions are executed serially in time, and their corresponding results are voted based on the derived learned weights. The proposed weighted voting module generates the final output based on the results and their weights. In the proposed weighted voting module, a reward/punishment strategy is employed to provide the weight of each version of execution indicating its effectiveness in the final output. To this aim, in the method defined for each version of execution, a weight is defined according to its correction capability confronting several faulty scenarios. Thus, this weight defines the reliability of the temporal results as well as their effect on the final result. The final result is generated bit by bit based on the weight of each version of execution and its computed result. Based on the proposed learning scheme, positive or negative weights are assigned to execution versions. These weights are derived in bit level based on the capability of execution versions in mitigating permanent faults in several fault injection scenarios. Thus, our proposed method is low cost and more efficient compared to related research which are mainly based on information and hardware redundancy due to employing time redundancy and static learning approach in correcting permanent faults. Several experiments are performed to reveal the efficiency of our proposed approach based on which FT-EALU is capable of correcting about $$84.93\%$$ and $$69.71\%$$ of permanent injected faults on single and double bits of input data. 

/pdf/ft-ealu-fault-tolerant-arithmetic-and-logic-unit-for-1a33gbsg.pdf

FT-EALU: fault-tolerant arithmetic and logic unit for critical embedded and real-time systems

In many countries like India, farming is done using indigenous methods. Because of lack of proper knowledge in our farmers, the state of the agricultural sector becomes even more critical. Since the farming methodologies rely mostly on weather forecasts and predictions which might not be foolproof, most often the farmers incur huge losses leading to debts and mass farmer suicides. Adequate soil moisture, soil quality, air quality, and proper irrigation play a major role in the yield of crops, and hence, such factors cannot be overlooked. A major concern now is the exploding population due to which the agricultural supplies are not meeting the ever-increasing demand. The world's population is expected to cross nine billion marks by 2050 due to which the agricultural supply should increase at least by 70% to meet the requirement. To achieve this, it's necessary to monitor the plant growth at all stages starting from sowing until cultivation.

Sumit Pahuja

Papers

Design of Parity Preserving Arithmetic and Logic Unit using Reversible Logic Gates

Real-Time Crop Monitoring in Agriculture