VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. 

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.

System-on-Chip Test Architectures: Nanometer Design for Testability

Intellectual property cores pose a significant test challenge. The core supplier may not give any information about the internal logic of the core, but simply provide a set of test vectors for the core which guarantees a particular fault coverage. If the core is embedded within a larger design, then the problem is how to apply the specified test vectors to the core and how to test the user-defined logic around the core. A simple and fast solution is to place a full isolation ring (i.e., boundary scan) around the core, however, the area and performance overhead for this may not be acceptable in many applications. This paper presents a systematic method for designing a partial isolation ring that provides the same fault coverage as a full isolation ring, but avoids adding MUXes on critical timing paths and reduces area overhead. Efficient ATPG techniques are used to analyze the user-defined logic surrounding the core and identify a maximal set of core inputs and outputs (that includes the critical timing paths) that do not need to be included in the partial isolation ring. Several different partial isolation ring selection strategies that vary in computational complexity are described. Experimental results are shown comparing the different strategies.

https://users.ece.utexas.edu/~touba/research/vts97a.pdf

Testing embedded cores using partial isolation rings

Publisher Summary This chapter discusses design for testability (DFT) techniques for testing modern digital circuits These DFT techniques are required in order to improve the quality and reduce the test cost of the digital circuit, while at the same time simplifying the test, debug and diagnose tasks The chapter also investigates that whether a design is implemented in a test-friendly manner and to recommend changes in order to improve the testability of the design for achieving the goals It also identifies scan design rule violations and understands the basics for successfully converting a design into a scan design This chapter describes the basic DFT concepts and methods for performing testability analysis It also briefly discusses DFT techniques, scan design, and DFT methodology including popular scan cell designs, scan architectures, scan design rules, scan design flow, and special-purpose scan designs Finally, advanced DFTtechniques for use at the register-transfer level (RTL) are presented in order tofurther reduce DFT design iterations and test development time

Design for Testability

The Crosscheck grid of sense and probe lines provides a convenient mechanism for addressing a large number of nodes in the circuit. This testpoint grid was previously used to observe internal nodes in the circuit. In this paper we describe a technique that makes use of the same grid to also selectively inject signals into storage elements. The technique is based on a novel design of a grid-addressable latch element, called Cross-Controlled Latch (CCL), which allows all flip-flops in the circuit to be deterministically controlled. The combination of massive observability provided by the Crosscheck test matrix and controllability completely solves the static ASIC functional test problem. In addition to the basic technique, we will discuss its area and performance impact. We present results on two real designs, as well as on several pathological cases which are known to be difficult to test. I. Introduction Automatic test generation for sequential circuits is known

ATPG based on a novel grid-addressable latch element

During application of a sequence of design verification patterns at the primary input pins of a sequential circuit IC, a test vector is spliced between patterns to test for a fault condition. As design verification patterns are applied in sequence, the state of the sequential circuit changes. To test for a select fault condition, the sequential circuit needs to be in a desired state. While in such desired state, a test vector is applied and select internal circuit element responses are monitored. If the desired state occurs during a sequence of design verification patterns, then the test vector is applied between successive patterns before the IC clock has a transition. By applying the test signal, monitoring the response, then reapplying the design verification pattern before the clock changes, the IC subsequent state which would occur had the test vector been omitted still occurs. If a desired state does not occur during the sequence of design verification patterns, then a select state similar to the desired state is identified. When such select state occurs, control signals are applied through internal test points to force a state change to the desired state. Thereafter, the appropriate test vector is applied and the response is monitored to check the fault condition. All such steps occur before a clock transition so that the state and design verification pattern occurring at the beginning of the clock cycle, also occur before the next transition to the clock cycle. Accordingly, the design verification pattern sequence is not invalidated.

Method for testing a sequential circuit by splicing test vectors into sequential test pattern

An IC has local test circuitry including a test point array, instruction register, data register, probe line drivers and control/sense line drivers/receivers To test the IC, the instruction register is loaded initiating the test circuitry to address select test points to receive control signals and to address other select test points at which response signals are to be sensed Control signals are produced from the data register contents The data register contents are derived as a function of the prior contents of the data register and a bit pattern formed from response signals of select test points According to one embodiment, the prior contents are exclusively or'ed with the bit pattern of response signals to derive the new data register contents A continuous test is performed by using prior response signals exclusively OR'ed to data register contents so as to generate subsequent control signals Predesigned test sequences enable fast continuous testing of the IC

Susheel J. Chandra

Papers

ATPG based on a novel grid-addressable latch element

Method for testing a sequential circuit by splicing test vectors into sequential test pattern

Method and apparatus for locally deriving test signals from previous response signals

CrossCheck An Innovahe Testab;l;ty Solution