Modern transmission line theory and applications

Continuous shrinking of the size of CMOS technology leads to extremely fast devices, but the resulting interconnect structures impose so many parasitic effects that the advantage of extremely scaled and ultrahigh-speed transistors would be completely overshadowed if appropriate remedial steps are not taken. This requires an accurate and efficient estimation of interconnect parasitics and analysis of their impact on integrated circuit performance. This paper proposes a new delay model for RLC interconnect networks in CMOS technology based on a second order approximate transfer function. The proposed modeling approach includes all possible scenarios (complex poles, real poles, and double poles) in the interconnect model. Simulation results show that the proposed delay model is almost independent of the ratio of ${V}_{\mathrm { {out}}} / V_{\mathrm { {in}}}$ , and the driver resistance has significant impact on the delay. The simulation results also show that the real pole model provides better accuracy and is much faster than the complex pole model. This observation would help to optimize the values of interconnect parasitics for faster operation.

Analytical Models of High-Speed RLC Interconnect Delay for Complex and Real Poles

System-Level Design of Timing-Sensitive Network-on-Chip Based Dependable Systems

This paper presents a novel analytical closed form expression for the crosstalk noise voltage and delay in the presence of skin effect. With the rapid development of high frequency IC technology, a number of high-speed interconnect effects, such as ringing, signal delay, distortion, reflections, and crosstalk, need to be considered during the IC design. Skin effect is one of the high frequency phenomena that can adversely affect the distribution of current density in interconnect because the problem associated with the skin effect is that it attenuates the high frequency components of a signal more than that of the low frequency components. On-Chip interconnect has become the dominant factor in deep sub-micrometer (DSM) integrated circuits (ICs). With increasing levels of on-chip integration, more functional units are integrated onto a single die, such as a multi-core microprocessor and a system-on-chip. Global interconnect, which acts as a communication media among these functional units, plays an increasingly important role and can significantly limit the performance of advanced systems. Accurate noise and delay modelling for RLC lines is thus critical for timing and signal integrity analysis. Skin effect basically affects the resistance and also the inductance, which in turn affects the system integrity in particular and its response as a whole. The current distribution inside the conductor changes as frequency increases. These changes produced in the conductors are known as skin effect. Till now the skin effect has been neglected for the modelling of the on-chip interconnects. But with the increase in frequency to the GHz range, the skin effect has become prominent in performance parameter modelling. In this paper, firstly a crosstalk noise formula for on chip VLSI interconnect has been proposed without considering the skin effect. The voltage response at the output node is analytically derived and then the skin effect on the line resistance is analysed. In this work, the resistance variation due to the skin effect is considered in two wire transmission line model. An explicit closed form expression has been developed for the estimation of cross-talk noise voltage and delay. The correlation between the skin effect and the noise induced is also discussed. The simulation results justify the efficacy of the proposed crosstalk noise aware delay model in the presence of skin effect.

An explicit crosstalk aware delay modelling for on-chip vlsi rlc interconnect with skin effect

Delay and power are two major issues in design and synthesis of VLSI circuits which depends on different design parameters. In this paper, the relative study of propagation delay and power consumption of UDSM CMOS inverter is found considering the channel length below 100nm. The simulation results are taken for different technology (32nm, 45nm, 65nm and 90nm) with the help of Tanner (T-spice) simulation tool. The values of model parameters are used from current Berkeley Predictive Technology Model (PTM). Also the results are analyzed by varying load capacitance, supply voltage

Comparative study for delay & power dissipation of CMOS Inverter in UDSM range

In this paper, simple explicit delay and rise time expressions for uniformly distributed RC on-chip interconnect line are derived based on Elmore's approximations. Here, an n-cell RC ladder network with capacitive load is used. Transfer function for the n-cell RC ladder network is obtained by using the transmission line parameter matrix for each cell. In order to deduce the transfer function, the transmission line is modeled by a lumped parameter network. From this transfer function, explicit delay and rise time expressions are derived by using Elmore's definitions. The calculated delay and rise times by our proposed closed form expressions are compared with the results obtained by SPICE simulation for n=2, 3, 4, 5, 6, 7 cell ladder networks with capacitive load.

An explicit model for delay and rise time for distributed RC on-chip VLSI interconnect

In this paper, a closed form delay and power model of a CMOS inverter driving a resistive-inductive-capacitive load is presented. The model is derived from Sakurai’s alpha-power law and exhibits good accuracy. The model can be used for the design and analysis of the CMOS inverters that drive a large interconnect RLC load when considering both speed and power. Closed form expressions are also presented for the propagation delay and transition time which exhibit less than 15% error compared to the SPICE for a wide range of RLC loads. Explicit methods are also provided for modelling the short-circuit power dissipation of a CMOS inverter driving a RLC line. The average error is within 22% compared to SPICE for most practical loads. The resistive power dissipation has also been considered for various RLC loads which are accurate to within 9% to that of SPICE.

Closed form solution for delay and power for a cmos inverter driving rlc interconnect under step input

In high-speed nanometre VLSI technology, the on-chip interconnect delay plays an important role and is dominant compared to the gate delay. Hence, an accurate estimation of the on-chip interconnect delay dictates both performance and physical design optimization for high speed CMOS VLSI circuits. The interconnect is modelled as distributed segments which ensures the system order to be in millions. An accurate and detailed modelling requires large scale linear circuits to be analyzed. Accurate estimation of the propagation delay of such a large circuit is critical. Therefore, a method of reducing the circuit order (or size) is necessary in order to compute the propagation delay in a reasonable time period which might not be exact, but nearly exact delay estimate, as required from the designer's point of view. This paper presents a simple and yet accurate delay modelling approach using the Balanced Truncation Method (BTM) for the on-chip distributed RLC interconnects. The proposed delay can be estimated as a closed form from the state space model for an evenly distributed RLC truncated interconnects. The closed form has very low computation complexity of O(1), which may be extended for use not only in circuits, but also in various complex systems with transmission lines, networks or delay lines. The proposed model could result an error of as low as 9% when compared to that of the SPICE simulation.

A Closed Form Delay Estimation Technique for High Speed On-Chip RLC Interconnect Using Balanced Truncation Method

On-chip inductive effects are becoming predominant in deep submicron interconnects due to increasing clock speed, circuit complexity and an increase in interconnect length. In this paper, a novel closed form delay metric has been proposed for the on-chip VLSI RLC interconnect. The model has also been extended for the case when the time of flight of the input signal is comparable. It is started with a distributed RLC line model of the interconnect and analytically solved the resulting diffusion equation for the voltage response and 50% delay has been calculated and has been compared with SPICE delay and error is within 7%. The proposed method also calculates 50% delay by taking the time of flight into consideration and result is compared with SPICE and the average error has been found to be within 6%.

An Explicit Delay Model for On-Chip VLSI RLC Interconnect

This work proposes an accurate crosstalk noise estimation method in the presence of multiple RLC lines for the use in design automation tools. This method correctly models the loading effects of non switching aggressors and aggressor tree branches using resistive shielding effect and realistic exponential input waveforms. Noise peak and width expressions have been derived. The results obtained are at good agreement with SPICE results. Results show that average error for noise peak is 4.7% and for the width is 6.15% while allowing a very fast analysis.

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Susmita Sahoo

Papers

An explicit model for delay and rise time for distributed RC on-chip VLSI interconnect

Closed form solution for delay and power for a cmos inverter driving rlc interconnect under step input

A Closed Form Delay Estimation Technique for High Speed On-Chip RLC Interconnect Using Balanced Truncation Method

An Explicit Delay Model for On-Chip VLSI RLC Interconnect

Accurate Crosstalk Analysis for RLC On-Chip