A semiconductor device includes capacitors connected in parallel. Electrode active portions and a discharge active portion are defined on a semiconductor substrate, and capping electrodes are disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion. A lower interlayer dielectric covers the entire surface of the semiconductor substrate. Electrode contact plugs respectively contact the capping electrodes through the lower interlayer dielectric, and a discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts the electrode contact plugs and the discharge contact plug.

Semiconductor devices and methods of fabricating the same

A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

A semiconductor device in which MRAM is formed in a wiring layer A contained in a multilayered wiring layer, the MRAM having at least two first magnetization pinning layers in contact with a first wiring formed in a wiring layer and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layers in a plan view, and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layer situated over the non-magnetic layer.

Semiconductor device and method of manufacturing the semiconductor device

A method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is described. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the substrate and in a memory area of the substrate and providing node contact plugs to node contact regions within the substrate in the memory area. Thereafter, capacitors are fabricated in a twisted trench in a self-aligned copper process.

Method of fabricating an embedded DRAM for metal-insulator-metal (MIM) capacitor structure

In manufacturing a semiconductor device, static electricity is generated while contact holes are formed in an interlayer insulating film by dry etching. Damage to a pixel region or a driving circuit region due to travel of the static electricity generated is prevented. Gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit, the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT. The driving circuit TFT is thus prevented from suffering electrostatic discharge damage.

Semiconductor Device and Method of Manufacturing the Same

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of being constituted only of a small scale digital circuit, changing spread bands of frequency after it is mounted on a substrate by a designer of the substrate and executing EMI countermeasure without changing an LSI circuit by changing frequency bands based on the result of EMI measurement SOLUTION: This semiconductor integrated circuit device is provided with a delay array 011 to input a clock and to generate plural clocks, a clock selecting circuit 026 to input the plural clocks and a control circuit 020 to select and control a clock to be outputted from the clock selecting circuit 026 from the plural clocks

Suzuki Masaru

Papers

Semiconductor integrated circuit device