Hardware for executing matrix arithmetic and signal processing algorithms at high speeds is in great demand in many real-time and scientific applications. With the advent of VLSI technology, large numbers of processing elements which cooperate with each other at high speed have become economically feasible. Since any functional error in a high-performance system may seriously jeopardize the operation of the system and its data integrity, some level of fault tolerance must be incorporated in order to ensure that the results of long computations are valid. Since the major computational requirements for many important real-time signal processing tasks can be reduced to a common set of basic matrix operations, the development of a unified fault-tolerant scheme for matrix operations can solve the problems of both reliable signal processing and reliable matrix operations. Earlier work proposed a low-cost checksum scheme for fault-tolerant matrix operations on multiple processor systems. However, this scheme can only correct errors in matrix multiplication; it can detect, but not correct, errors in matrix-vector multiplication, LU decomposition, matrix inversion, etc. In order to solve these problems with the checksum scheme, a very general matrix encoding scheme is proposed in this paper to achieve fault-tolerant matrix arithmetic and signal processing with linear arrays, which are believed to hold the most promise in VLSI computing structures for their flexibility, low cost, and applicability to most of the interesting algorithms. This proposed technique is, therefore, a very cost-effective encoding technique to achieve fault-tolerant matrix arithmetic and signal processing on highly concurrent VLSI computing structures.

Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures

The past decade has seen the development of productive fast electronic digital computers. Significant problems have been solved and significant numerical experiments have been executed. Moreover, as expected, a growing number of important problems have been recorded which are not practicably computable by existing systems. These latter problems have provided the incentive for the present development of several large scale digital computers with the goal of one or two orders of magnitude increase in overall computational speed.

Organization of Computer Systems-the Fixed Plus Variable Structure Computer

This paper is a brief introduction to a new class of computers, the reconfigurable massively parallel computer. Its most distinguishing feature is the utilization of the reconfigurability of the interconnection network to establish a network topology well mapped to the algorithm communication graph so that higher efficiency can be achieved, and to remove faulty processors from the network so that the system operation can be kept uninterrupted while maintaining the same or slightly degraded efficiency. Several existing reconfigurable single instruction multiple data (SIMD) parallel architectures and their reconfiguration mechanism are described, the effectiveness of algorithm mapping, through reconfiguration, is demonstrated, and fault-tolerant schemes via reconfiguration are discussed. >

Reconfigurable SIMD massively parallel computers

A standardizable LSI microprocessor with on-chip configuration control directed by operating-system commands promises a series of computer sets dynamically matched to user-program characteristics.

Dynamic Architectures: Problems and Solutions

Communication paths between parallelarchitecture resources can be reconfigured to suit new computational structures; however, this capability places new demands on efficient architecture use. In the past decade a significant amount of research focused on the development of highly parallel architectures.' Progress in research on Very-Large-Scale-Integrated-Circuit (VLSI) and Very-High-Speed-Integrated-Circuit (VHSIC) technologies is making it feasible to consider the construction ofcomplex parallel architectures that comprise a number of processors communicating by means of a high-bandwidth interconnection network. (Two often-proposed organizations, the processor-memory and the processor-processor network, are shown in Figure 1.) By utilizing a large number of such processors, these architectures have the potential to provide enormous throughputs leading to the computation of processes previously considered impractical due to their complexity. However, the availability of multiple processors alone is not sufficient to ensure practical solutions to computationally intensive tasks. One of several modes of operation may be de-

Reconfiguration Strategies for Parallel Architectures

The authors report on parallelism and array processing, presenting a comprehensive survey of supercomputing as a concept. The chapter on data flow computing describes an alternative approach to supercomputing based on data flow. The chapter on implementing reliable distributed supercomputing systems focuses on the issues of reliability of distributed supercomputer networks. The chapter on solutions methods for data and program allocations in supercomputer networks addresses the problem of data and program allocation in distributed high-performance data bases. The last chapter covers image processing application in supercomputers.

Designing and Programming Modern Computers and Systems

This paper introduces concurrent reconfiguration techniques that perform fast reconfiguration of a multicomputer network into the following network structures: K-rooted trees, stars, and rings with selectable periods. These structures prove to be very efficient for high-speed, real-time applications. The techniques introduced are based on shift register theory and are performed by special shift registers residing in each network node and called shift registers with variable bias.The technique discussed in this paper are implemented in the system with dynamic architecture that is now under construction by Dynamic Computer Architecture, Inc.The time of the network reconfiguration equals that of one clock period, since to perform reconfiguration into a new network structure, each network node should execute only two logical operations---one-bit shift and mod 2 addition.

Reconfigurable multicomputer networks for very fast real-time applications

The main characteristic of most powerful parallel systems is that their architecture is oriented towards specific types of problems to be computed. Such an orientation limits the range of tasks that can be effectively solved. As a result, systems are produced in small quantities which must bear all the costs of software and hardware development, and which are, as a result, very expensive. This slows down the computerization of many other complex problems just because they require that new high cost parallel systems be manufactured for their computation.

Adaptation properties for dynamic architectures

http://www.computer.org/csdl/proceedings/afips/1979/5087/00/50870543.pdf

This paper considers a state assignment which permits one to obtain two different realizations of a sequential machine (sm). First, as a result of this assignment we obtain a double shift-register realization of an sm by means of p pairs of shift-registers, each pair of registers having the same number of stages a i (i = 1,...,p). Such realizations are called multiple-variable-length-shift-register-realizations (MVL-SRR's). Second, this state assignment permits us to obtain multimodule type iterative realizations made by means of p different module types, each of them being copied a i times (i = l,...,p). We call these realizations multiple-variable-length-iterative-realizations (MVL-IR's). Thus any MVL-SRR or MVL-IR is uniquely specified by γ p , = (a 1 ,...,a p ,).

Svetlana P. Kartashev

Papers

Designing and Programming Modern Computers and Systems

Reconfigurable multicomputer networks for very fast real-time applications

Adaptation properties for dynamic architectures

Adaptation properties for dynamic architectures

Theory and Implementation of p-Multiple Sequential Machines