Silicon nanowire (SiNW) structures are the essential foundations of the next generation highly efficient and lowcost electronic devices because of their specific chemical, optical, and electrical properties. In recent decades, the production of pure Si NW arrays with the ability to tune the wire density and dimensions has been intensively studied. This paper demonstrates the performance of silicon nanowire (Si NW) array based cylindrical gate all around (GAA) MOSFET using quantum transport model in lower technology nodes. With an improvement in drain current and lower value of threshold voltage, the proposed structure is proving itself as one of the leaders in GAA MOSFET family. Again the study includes the effect of variation in gate voltage on the electrostatic potential of individual nanowires and the potential developed at the channel-source/drain interface. The improved ON current with superior electrostatic integrity due to silicon pillars is showing the possibility of this device towards future development in CMOS technology. Finally, the article includes the integration of nMOS and pMOS to realize the CMOS inverter for high speed and noise immune characteristics.

Nanowire Array-based MOSFET for Future CMOS Technology to Attain the Ultimate Scaling Limit

This work represents a unique GAA MOSFET with metal work-function variations (WFVs) and ferroelectric material as dielectric. A random distribution of metal grain (TiN) with grain size varied from 7nm to 10 nm is studied extensively. The potential distribution is studied by pushing the size of the device into lower technology node. The proposed structure exhibits improved drain current with lower threshold voltage. Additionally, comparative analysis on drain current of proposed structure with dual material GAA MOSFET and junction less GAA MOSFET is carried out. Irrespective of the type of the device and material used, the proposed device exhibits lower subthreshold swing (< 60 mV/decade), improved switching ratio (IOn/IOff) due to amalgam of ferroelectric and GAA structure.

Performance Analysis of Ferroelectric GAA MOSFET with Metal Grain Work Function Variability

Short channel effects (SCEs) along with mobility degradation has a great impact on CMOS technology below 100 nm. These effects can be overcome by using gate and channel engineering techniques which will improve mobility of the charge carriers, thus eventually improving drain current and trans-conductance of the device. In this work, the speed of operation for DG MOSFET is improved by reducing the channel length where dual-material gate-stack is deployed to avoid the drain-induced barrier lowering (DIBL) and hot carrier effects. In the presented device, the metal closer to the source and drain has higher and lower work function, respectively which causes a significant decrement in the peak electric field at the drain side and so the SCEs. The carrier mobility is also increased due to enhanced electric field in the channel, near the source, caused by higher work function gate material which, in turn, increases the MOSFET’s driving current. The screening effect reducing SCEs and an increment in the acceleration of the charge carriers in the channel are mainly attributed due to higher and lower threshold voltage found near the source and drain, respectively.

Performance Analysis of Gate-Stack Dual-Material DG MOSFET Using Work-Function Modulation Technique for Lower Technology Nodes

Cryogenic Analysis of Junctionless Nanowire MOSFET during Underlap in Lower Technology Nodes

An insight into the Performance Analysis of GAA MOSFET for Different Dielectrics at Cryogenic Temperatures

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T.Akhil Babu

Papers

Performance Analysis of GAA MOSFET for Lower Technology Nodes.