A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low resistance regions.

High-breakdown-voltage semiconductor device

A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity region and from there to a relatively high resistivity epitaxially formed region which is deposited on a high conductivity substrate. The drain electrode may be either on the opposite surface of the chip or laterally displaced from and on the same side as the source regions. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without effecting the breakdown voltage of the device. The breakdown voltage of the device is substantially increased by forming a relatively deep p-type diffusion with a large radius in the n-type epitaxial layer beneath each of the sources.

High power MOSFET with low on-resistance and high breakdown voltage

An electrical circuit device made in integrated monolithic form has low level operating characteristics of a MOS device and high level operating characteristics of a Triac. The structure includes two double diffused MOS transistors which have merged drain regions. At higher voltage and current levels a lateral Triac structure is triggered by the MOS devices. Alternatively, separate terminal contacts can be made to the P and N regions comprising the MOS transistor source and channel regions with the Triac triggered conventionally by an externally applied control voltage.

Monolithic semiconductor switching device

A vertical MOSFET includes source and gate electrodes on a major semiconductor surface, and a drain electrode on an opposing semiconductor surface. A shield electrode is disposed in proximity to the gate electrode so as to minimize feedback capacitance between the gate electrode and drain region. Additionally, the shield electrode increases the level of space charge limited current that can be supported in the drain region, and minimizes current crowding in the device.

Vertical MOSFET with an aligned gate electrode and aligned drain shield electrode

A power metal-oxide-semiconductor field-effect transistor (MOSFET) having high switching speed capabilities is shown. The high switching speed is facilitated by narrow channel length which is defined by the difference in lateral diffusion junctions of the P substrate and N source diffusions. The high current capability is produced by the large channel width. The high voltage capability is caused by the use of FET substrate P diffusions designed to be located apart from one another by very small distances. Unbiased or floating P diffusions are designed to flank the outer peripheries of P substrate diffusions. The close proximity of the adjacent P substrate diffusions reduces the electric field in the curvature portion of the P diffusion junctions in the N - silicon body at their inner peripheries, while the presence of the unbiased P diffusions at the appropriate distance from the outer peripheries of P substrate diffusions reduces the electric field in the curvature region of the P substrate diffusions at their outer peripheries. The N silicon body forms the drain region.

Power field effect transistors

High voltage, high frequency metal oxide semiconductor device having a precisely controlled channel extending to the surface and in which a metallization overlies a thick insulating layer and substantially covers the depletion region in the drain for breakdown voltage control.

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Papers

High voltage, high frequency double diffused metal oxide semiconductor device