Structural reliability of integrated circuit (IC) chips in electronic packages continues to be a major concern due to ever-increasing die size, circuit densities, power dissipation, operating temperatures, and the use of a wide range of low-cost packaging materials. A powerful method for experimental eval- uation of silicon die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, a review is made of the state-of-the-art in the area of silicon piezore- sistive stress sensor test chips. Developments in sensor theory, calibration methods, and packaging applications are presented. In the absence of die failure, packaging-induced stresses result in changes in the parametric performance of circuitry on the die, and the theory discussed here can be used to predict such changes. Index Terms—Electronic packaging, piezoresistive, stress sensor, test chip.

Silicon piezoresistive stress sensors and their application in electronic packaging

CMOS analog stress sensor circuits based upon the piezoresistive behavior of MOSFET's are presented. On the [100] surface, these circuits provide temperature-compensated outputs that are proportional to the in-plane normal stress difference (/spl sigma/(11)'-/spl sigma//sub 22/') and the in-plane shear stress /spl sigma//sub 22/'. The circuits provide high sensitivity to stress, well-localized stress-state measurement, and direct voltage or current outputs that eliminate the need for tedious /spl Delta/R/R measurements required with more traditional resistor rosettes. The theoretical and experimental results also provide design guidance for calculating and minimizing the sensitivity of traditional analog circuits to packaging-induced die stress.

CMOS stress sensors on [100] silicon

Thermal-mechanical stresses occur in plastic IC packages. These stresses affect Hall plate magnetic sensitivity via the piezo-Hall effect. In this paper the short and long-term stability problems of Hall plates encapsulated in SOP and TSSOP packages are considered. A sensitivity shift is observed when reflow soldering, temperature cycling, or humidity testing are performed. Moreover, this shift is not stable in time and a slow relaxation is observed. This parameter shift is seen as a serious reliability failure of the Hall plates. Sensitivity drift is related to packaging stress drift due to the viscoelastic flow of the molding compound. The normal in-plane stress drift is calculated from the high-accuracy magnetic measurements.

Short and long-term stability problems of Hall plates in plastic packages

Bandgap references, packaged in plastic, have been known to shift in voltage, a pre-package to post-package voltage variation. This package shift has been analytically discussed and experimentally investigated in this paper. The culprits for such a variation are the package-induced stresses present once the reference is encapsulated. Systematic voltage shifts can range from -3 to -7 mV, and is closely related to package type and processing. Major emphasis has been placed on reducing the random package-shift component, since systematic package shift can be trimmed and its temperature coefficient compensated. The package shift is seen to have a systematic positive temperature coefficient; its effects are mitigated as temperature increases. In summary, results of the study show that die-surface planarization techniques and mechanically elastic compliant layers between the die and the package reduce random as well as systematic package shifts. In particular, systematic variations improved from -5 to -2 mV (0.4% to 0.17% bandgap error) and three-sigma (3/spl sigma/) variations improved from 8 to 4 mV (0.67% to 0.33% bandgap error) when adding a 15-/spl mu/m mechanically compliant layer between the die and the package.

Voltage shift in plastic-packaged bandgap references

NEPP program objectives are to: (1) Access the reliability of newly available electronic parts and packaging technologies for usage on NASA projects through validations, assessments, and characterizations, and the development of test methods/tools; (2)Expedite infusion paths for advanced (emerging) electronic parts and packaging technologies by evaluations of readiness for manufacturability and project usage consideration; (3) Provide NASA projects with technology selection, application, and validation guidelines for electronic parts and packaging hardware and processes; nd (4) Retain and disseminate electronic parts and packaging quality assurance, reliability validations, tools, and availability information to the NASA community.

NASA Electronic Parts and Packaging Program

In molded DIP packaging die attach stresses and stresses due to the contraction of the molding compound lead to a complex state of stress on the die surface where active device elements are located. This paper summarizes experimentation to reduce the effects of packaging stresses upon offset voltage shift in a precision operational amplifier. Variables examined include circuit location, low stress mold compounds, silicone gel coatings, side braze versus molded DIP assembly and post assembly trim. >

T. Doan

Papers

Stress related offset voltage shift in a precision operational amplifier