Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

Characterization of soft errors caused by single event upsets in CMOS processes

We propose a quad-node ten transistor (10 T) soft error robust SRAM cell that offers differential read operation for robust sensing. The cell exhibits larger noise margin in sub-0.45 V regime and 26% less leakage current than the traditional soft error tolerant 12 T DICE SRAM cell. When compared to a conventional 6 T SRAM cell, the proposed cell offers similar noise margin as the 6 T cell at half the supply voltage, thus significantly saving the leakage power. In addition, the cell exhibits 98% lower soft error rate than the 6 T cell in accelerated neutron radiation tests carried out at TRIUMF on a 32-kb SRAM implemented in 90-nm CMOS technology.

A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability

Early in the deployment of the Advanced Simulation and Computing (ASC) Q supercomputer, a higher-than-expected number of single-node failures was observed. The elevated rate of single-node failures was hypothesized to be caused primarily by fatal soft errors, i.e., board-level cache (B-cache) tag (BTAG) parity errors caused by cosmic-ray-induced neutrons that led to node crashes. A series of experiments was undertaken at the Los Alamos Neutron Science Center (LANSCE) to ascertain whether fatal soft errors were indeed the primary cause of the elevated rate of single-node failures. Observed failure data from Q are consistent with the results from some of these experiments. Mitigation strategies have been developed, and scientists successfully use Q for large computations in the presence of fatal soft errors and other single-node failures.

Predicting the number of fatal soft errors in Los Alamos national laboratory's ASC Q supercomputer

Scaling transistor size to the scale of the nanometer coupled with reduction of supply voltage has made SRAMs more vulnerable to soft errors than ever before. The vulnerability has been accentuated by increased variability in device parameters. In this paper, we present an analytical model for critical charge in order to assess the soft error vulnerability of 6T SRAM cell. The model takes into account the dynamic behavior of the cell and demonstrates a simple technique to decouple the nonlinearly coupled storage nodes. Decoupling of storage nodes enables solving associated current equations to determine the critical charge for an exponential noise current. The critical charge model thus developed consists of both NMOS and PMOS transistor parameters. Consequently, the model can estimate critical charge variations due to variability of transistor parameters and manufacturing defects, such as resistive contacts and vias. In addition, the model can serve as a tool to optimize the hibernation voltage of low-power SRAMs or the size of MIM capacitor per cell in order to achieve a target soft error robustness. Critical charge calculated by the model is in good agreement with SPICE simulations for a commercial 90-nm CMOS process with a maximum discrepancy of less than 5%.

An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs

We propose a new built-in current sensor (BICS) to detect single event upsets (SEUs) in SRAM. The BICS is designed and validated for 100 nm process technology. The BICS reliability analysis is provided for process, voltage and temperature variations, and power supply noise. The BICS detects various shapes of current pulses generated due to particle strike. The BICS power consumption and area overhead are also provided. The BICS is found to be very reliable for process, voltage and temperature variations and under stringent noise conditions.

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An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories

We report on enhanced susceptibility for neutron-induced soft errors from accelerated testing of static random access memories (SRAMs), performed at Los Alamos National Laboratory. This enhancement is per bit of memory.

Soft error rate increase for new generations of SRAMs

We report on experimental SEU studies using thermal and high-energy neutrons, conducted at the TRIUMF facility, Vancouver. Different SRAM samples were used and many samples showed to be highly susceptible to thermal neutrons. Moreover, a considerable part of the total SEU-rate, at high altitudes as well as down at sea level, may be attributed to thermal neutrons for RAM based devices.

SEUs Induced by Thermal to High-Energy Neutrons in SRAMs

We report on a comparative study between two neutron facilities used for SEU studies, namely the Weapons Neutron Research facility at Los Alamos National Laboratory (a white neutron source), and the The Svedberg Laboratory in Sweden (a quasimono-energetic neutron source). The soft error rates generated from TSL are in excellent agreement with those from WNR. Moreover, an increase of the SER for small process technologies was observed.

A comparative study between two neutron facilities regarding SEU

This article approaches single-event upset (SEU) problems from the standpoint of experimental nuclear physics, with a focus on certain neutron experiments and neutron data essential for SEU studies. A review is given of some research programs, both basic and applied, that are strongly motivated by SEU applications. Some specific examples are presented from the The (short for Theodor) Svedberg Laboratory (TSL) in Uppsala, Sweden: First, using the quasi-monoenergetic neutron beam, SEU cross sections (of chips) are measured over the neutron energy range of 20-150 MeV. Data from the same technology generation, in general, can be fitted into a simple curve. Second, the particle origins of SEUs are discussed from the framework of neutron-nucleus spallation reactions.

Relations between basic nuclear data and single-event upsets

We report on irradiation induced SEU by high-energy protons and neutrons. The experiments were performed at The (odor) Svedberg Laboratory in Uppsala, Sweden, and at the Weapons Neutron Research (WNR) facility, Los Alamos, USA. A wide range of SRAMs were used to study the differences between proton and neutron induced SEUs at different energies

T. Granlund

Papers

Soft error rate increase for new generations of SRAMs

SEUs Induced by Thermal to High-Energy Neutrons in SRAMs

A comparative study between two neutron facilities regarding SEU

Relations between basic nuclear data and single-event upsets

A Comparative Study between Proton and Neutron Induced SBUs in SRAMs