A new method of packing the rectangles (modules) is presented with applications to IC layout design. It is based on the bounded-sliceline grid (BSG) structure. The BSG dissects the plane into rooms associated with binary relations ``right-to''and ``above'' such that any two rooms are uniquely in either relation. A packing is obtained through an assignment of modules on the BSG, followed by physical realization BSG-PACK. A simulated annealing searches for a good packing of all packings by changing the assignments. Experiments showed that hundreds of rectangles are easily packed in a small rectangle area (chip) with a quite good quality in area efficiency. A wide adaptability is demonstrated specific to IC layout design. Remarkable examples are: the chip is not necessarily rectangle, L-shaped modules and modules which are allowed to partially overlap each other can be handled.

http://www.cecs.uci.edu/~papers/compendium94-03/papers/1996/iccad96/pdffiles/07c_3.pdf

Module placement on BSG-structure and IC layout applications

A new method of packing the rectangles is proposed with applications to integrated circuit (IC) layout design. A special work-sheet, called the bounded-sliceline grid, is introduced. It consists of special segments that dissect the plane into rooms to which binary relations "right-of" and "above" are associated such that any two rooms are uniquely in either relation. A packing is obtained through an assignment of the modules into the rooms followed by a compaction procedure. Changing the assignments by swapping the contents of two rooms, a simulated annealing strategy is implemented to search for a good packing. Empirical results show that hundreds of rectangles are packed with a quite good quality in area efficiency. A wide adaptability is demonstrated specific to IC layout design. Ideas to handle a multilayer, nonrectangular chips with L-shaped modules are suggested.

Module packing based on the BSG-structure and IC layout applications

ALSYN (Analog Layout SYNthesis), a tool that synthesizes layout from netlist-level descriptions for a broad range of analog integrated circuits, is presented. User-defined rules derive partitioning and other control information, based on parameters and topology of the circuit. Equivalent control information can also be set individually, e.g. supplied in the input netlist by preceding circuit synthesis or during interactive use of the synthesis system. This flexible concept enables designers to incorporate their own reusable knowledge into the synthesis process and to explore design space with the assistance of ALSYN. A flexible module generator environment and easy technology database access offer support for extending the library of parameterized layout primitives with variable shapes. Fast tools for constructive placement, using the MinCut/slicing tree approach, and for maze-style routing and postprocessing, offer various means of coping with the individual requirements of most analog applications. >

ALSYN: flexible rule-based layout synthesis for analog IC's

A design methodology for the physical design of analog circuits is proposed. The methodology is based on the automatic generation of constraints on parasitics introduced during the layout phase from constraints on the functional performance of the circuit. In this novel performance-constrained approach, the parasitic constraints drive the layout tools to reduce the need for further layout iterations. Parasitic constraint generation involves (1) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the layout tools while meeting the performance constraints; and (2) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information in differential circuits. The constraint generator PARCAR is described and results presented for test circuits. >

Automatic generation of parasitic constraints for performance-constrained physical design of analog circuits

Presents a genetic approach to the placement problem of analog LSI chip designs. The emphasis is the application of our approach to a real-world problem. The objective of this problem is to minimize the overall net length and the layout area under many electrical constraints among elements, and under the condition of making the subsequent routing task easy. Our approach is based on a polycell placement style to make the routing easy and it minimizes several cost functions. Computational experiments show the efficiency of our genetic algorithm (GA) compared to the tabu search (TS). The concatenation of GA and TS, and a dynamic adjustment of the mutation rate are introduced, and their effectiveness is shown.

Polycell placement for analog LSI chip designs by genetic algorithms and tabu search

Efficient placement and routing algorithms are presented for the modules of a bipolar analog LSI. In the layout of an analog module, a grid-free technique is required to minimize the module area and geometric constraint observance is necessary for the circuit performance optimization. The placement algorithm determines cell positions observing the geometric constraints by vertex-grouping of the constraint graph representing the relative device positions in the input circuit diagram. The routing algorithm, based on the characteristic fine-grid maze router, allows grid-free routing and variable width routings observing the geometric constraints by dynamically generating wiring prohibition. These algorithms are applied to the design of the analog modules. Automatically designed modules are compact and the performance requirements are met. >

T. Hino

Papers

A high-packing density module generator for bipolar analog LSIs