A computer’s memory system is the repository for all the information the computer’s central processing unit (CPU, or processor) uses and produces. A perfect memory system is one that can supply immediately any datum that the CPU requests. This ideal memory is not practically implementable, however, as the three factors of memory capacity, speed, and cost are directly in opposition. By placing smaller faster memories in front of larger, slower, and cheaper memories, the performance of the memory system may approach that of a perfect memory system—at a reasonable cost. The memory hierarchies of modern general-purpose computers generally contain registers at the top, followed by one or more levels of cache memory, main memory (all three are semiconductor memory), and virtual memory (on a magnetic or optical disk). Figure 1 shows a memory hierarchy typical of today’s (1995) commodity systems. Performance of a memory system is measured in terms of latency and bandwidth. The latency of a memory request is how long it takes the memory system to produce the result of the request. The bandwidth of a memory system is the rate at which the memory system can accept requests and produce results. The memory hierarchy improves average latency by quickly returning results that are found in the higher levels of the hierarchy. The memory hierarchy usually reduces bandwidth requirements by intercepting a fraction of the memory requests at higher levels of the hierarchy. Some machines, such as high-performance vector machines, may have fewer levels in the hierarchy—increasing cost for better predictability and performance. Some of these machines contain no caches at all, relying on large arrays of main memory banks to supply very high bandwidth. Pipelined accesses of operands reduce the performance impact of long latencies in these machines. Cache memories are a general solution to improving the performance of a memory system. Although caches are smaller than typical main memory sizes, they ideally contain the most frequently accessed portions of main memory. By keeping the most heavily used data near the CPU, caches can service a large fraction of the requests without needing to access main memory (the fraction serviced is called the hit rate). Caches require locality of reference to work well transparently—they assume that accessed memory words will be accessed again quickly (temporal locality) and that memory words adjacent to an accessed word will be accessed soon after the access in question (spatial locality). When the CPU issues a request for a datum not in the cache (a cache miss), the cache loads that datum and some number of adjacent data (a cache block) into itself from main memory. To reduce cache misses, some caches are associative—a cache may place a given block in one of several places, collectively called a set. This set is content-addressable; a block may be accessed based on an address tag, one of which is coupled with each block. When a new block is brought into a set and the set is full, the cache’s replacement policy dictates which of the old blocks should be removed from the cache to make room for the new. Most caches use an approximation of least recently used

Memory systems

A three-state output circuit is disclosed. The three-state output circuit is comprised of a phase-splitter transistor, a pull-up transistor and a pull-down transistor and further comprised of a control circuit which operates to make the transistors active or non-active. At least one of said transistors is connected to the control circuit via a newly employed PNP transistor through its emitter and base. The collector thereof is connected to a ground point of the three-state output circuit.

Three-state output circuit

A 16times6-bit read-only memory (ROM), employing an architecture suitable for use as a phase to amplitude converter for direct digital synthesizers (DDS), has been implemented in InP double heterojunction bipolar transistor (DHBT) technology. The ROM uses a -3.8 V power supply and dissipates 1.13 W of power. The ROM is implemented in a test circuit that includes an 8-bit accumulator and a 6-bit digital-to-analog converter (DAC) to facilitate demonstration of high-speed operation. The maximum operating clock frequency is measured to be 36 GHz

36-GHz, 16 $\times$ 6-Bit ROM in InP DHBT Technology Suitable for DDS Application

A photoelectric-conversion device including at least two memory-cell units for a single sensor-cell unit is provided. A reset noise generated due to initialization of the sensor-cell unit is written into each of the memory-cell units at one time.

Photoelectric conversion device

Reseau matriciel d'elements semi-conducteurs, par exemple diodes de Schottky comprenant des cathodes reliees a des lignes verticales (BL) et des anodes reliees a des lignes horizontales (L). matrix array of semiconductor elements, for example Schottky diodes having cathodes connected to vertical lines (BL) and anodes connected to the horizontal lines (L). Les diodes d'une colonne dans le reseau sont reparties en groupes, connectees a un groupe de lignes (L1-1) a (L1-7), et les cathodes dans un groupe sont disposees dans deux zones (20-1) et (20-2) associees a des regions sous-collecteurs (21-1) et (21-2), pour la colonne (BL-1) s'etendant a partir des extremites du groupe jusqu'au dessous des positions rencontrees occupees par des diodes les plus proches du point milieu du groupe. The diodes in a column in the network are divided into groups, connected to a group of lines (L1-1) to (L1-7) and cathodes in a group are arranged in two zones (20-1) and ( 20-2) associated with sub-collector regions (21-1) and (21-2) to the column (BL-1) extending from the ends of the group to below encountered positions occupied by Nearest diodes the midpoint of the group. Deux ensembles (22-1, 23-1) et (22-2, 23-2) aux extremites et un court-circuit (24) permettent de relier les deux zones entre elles. Two sets (22-1, 23-1) and (22-2, 23-2) at the ends and a short circuit (24) used to connect the two areas therebetween. - Application aux memoires mortes ou matrices ET ou OU de reseau logique programmable. - Application to ROMs or matrices AND or OR programmable logic array.

Matrix array of semiconductor elements

A monolithic, fully-decoded 1024-bit read-only memory, with less than 50-ns access time and 350-mW power dissipation, will be discussed. The ROM can be bit-organized with a coincident select structure to minimize pin count and address decoders.

T. Hornak

Papers

Design considerations for a high-speed bipolar READ-ONLY memory