Next-generation high data rate wireless communication systems offer completely new ways to access information and services. To provide higher data speed and data bandwidth, RF transceivers in next-generation communications are expected to offer higher RF performance in both transmitting and receiving circuitry to meet quality of service. The semiconductor device technologies chosen will depend greatly on the tradeoffs between manufacturing cost and circuit performance requirements, as well as on variations in system architecture. It is hard to find a single semiconductor device technology that offers a total solution to RF transceiver building blocks in terms of system-on-chip integration. The choices of device technologies for each constituent component are important and complicated issues. We review the general performance requirement of key components for RF transceivers for next-generation wireless communications. State-of-the-art high-speed transistor technologies are presented to assess the capabilities and limitations of each technology in the arena of high data rate wireless communications. The pros and cons of each technology are presented and the feasible semiconductor device technologies for next-generation RF transceivers can be chosen upon the discretion of system integrators.

Device technologies for RF front-end circuits in next-generation wireless communications

An InGaP heterojunction-bipolar-transistor (HBT) power amplifier with the best linearity and high reliability is presented in this paper for use in wireless digital mobile communication systems. We optimized the linearity of a novel HBT device and investigated its reliability. Using SILVACO software, we performed a simulation of the HBT device. The best linearity, which was revealed for the device with a capacitance ratio Cbc (0/6 V), is 1.25 at a BVceo of 22 V. After the device was fabricated, a reasonably high PAE, i.e., ~ 55%, was obtained at 2.0 GHz, and an adjacent channel power ratio of over -48 dBc was achieved. In the reliability testing, the device, which was stressed at Vce = 3 V and JC = 25 kA/cm2 under 85°C ambient temperature and 85% humidity, showed no failure for more than 1100 h. No significant beta degradation was observed under an extreme current JC = 200 kA/cm2 stress under wafer-level electrical/thermal overstress tests.

Performance of High-Reliability and High-Linearity InGaP/GaAs HBT PAs for Wireless Communication

This paper explains how the adjacent-channel-leakage-power ratio (ACLR) of power amplifiers (PAs) can be reduced by using gain-expansion amplifiers in tandem and generating anti-phase intermodulation distortion (IMD) in the driver stage to cancel the IMD in the output stage. The power-added-efficiency (PAE) can thus be increased by using near-class-B-biased driver- and output-stage amplifiers, which inherently have gain-expansion characteristics and high PAE at low output power as well as at maximum output power. At a supply of 3.5 V and an output power of 27.1 dBm, the fabricated PA with a quiescent current of only 19.8 mA exhibited a PAE of 44%, a gain of 25.2 dB, and an ACLR of less than -38.0 dBc. This is state-of-the-art performance for a two-stage W-CDMA PA with an extremely low quiescent current.

A 20-mA quiescent current two-stage W-CDMA power amplifier using anti-phase intermodulation distortion

This paper explains a power-effective linearization technique for power amplifiers (PAs) having gain-expansion characteristics. A new on-chip dynamic-gain-deviation cancellation circuit improves the adjacent-channel-leakage-power ratio (ACLR) for a W-CDMA signal by 11 dB. At a supply of 3.5 V and an output power of 26.9 dBm, a fabricated PA with a quiescent current (Iq) of 19 mA exhibited a power-added efficiency of 50%, a gain of 26 dB, and an ACLR of -40 dBc. Furthermore, when we applied this technique to a PA with Iq of only 10-mA, this PA also satisfied the W-CDMA criteria.

50% PAE 20-mA quiescent current W-CDMA power amplifier with on-chip dynamic-gain linearizer

A true enhancement-mode junction pseudomorphic HEMT (JPHEMT) with a high threshold voltage (V/sub th/) Of +05 V was developed for single-supply power amplifiers The novel JPHEMT exhibits an extremely low standby leakage current The leakage current at 25/spl deg/C is 22/spl times/10/sup -10/ A/mm and even at 85/spl deg/C is 86/spl times/10/sup -9/ A/mm It is suggested that the leakage current is the lowest among reported enhancement-mode FETs Moreover, the novel JPHEMT exhibits a high turn-on voltage (V/sub F/) of 13 V at 1 mA/mm, which is 100 mV higher than that of a conventional JPHEMT The PA module performance for 195 GHz W-CDMA systems, under conditions of V/sub DS/ of 35 V and an adjacent channel leakage power ratio (ACLR) of -37 dBc, demonstrated an output power (P/sub out/) of 265 dBm, an associated gain (Gain) of 26 dB and a power added efficiency (PAE) of 47% The standby leakage current at gate-to-source voltage (V/sub GS/) of 0 V was less than 1 /spl mu/A even at 85/spl deg/C This high RF-performance, with extremely low leakage current results, indicate that the novel JPHEMT has single-supply amplifier capability

Low standby leakage current power amplifier module made with junction PHEMT technology

This paper reports on an InGaP/GaAs HBT with a GaAs/InGaP composite collector for a GSM power amplifier. The GaAs/InGaP composite collector enables the device to pass a ruggedness test with SWR=10:1 at V/sub CE/ >5 V, keeping the total collector thickness of around 900 nm and with a high power added efficiency (PAE). The load-pull measurement results for multi-cell HBTs with total emitter size of 7200 /spl mu/m/sup 2/ reveals a PAE of 74% at Pout=35 dBm and V/sub CE/=3.5 V for the composite collector.

A composite-collector InGaP/GaAs HBT with high ruggedness for GSM power amplifiers

An enhancement-mode power heterojunction FET utilizing a re-grown p/sup +/-GaAs gate (p/sup +/-gate HJFET) was developed for cellular applications. The p/sup +/-gate HJFET exhibited a high maximum drain current of 400 mA/mm and a gate forward turn-on voltage of 1.15 V with threshold voltage (V/sub T/) of +0.5 V. A small V/sub T/ standard deviation of 20 mV was obtained. The 32 mm gate width device has an extremely low off-state leakage current of 0.02 /spl mu/A at drain-to-source voltage (V/sub ds/) of 3.0 V and gate-to-source voltage of 0.0 V and at RT. Under single 3.2 V operation, the 32 mm device delivered 35 dBm output power, 11.9 dB associated gain and 73% power added efficiency at 950 MHz. Even operated at V/sub ds/ of 1.0 V, the device exhibited a high PAE of 70%. The developed p/sup +/-gate HJFET is promising for no drain bias switches and single voltage operation power amplifiers.

http://ieeexplore.ieee.org/iel5/8599/27270/01212469.pdf

T. Ishigaki

Papers

A composite-collector InGaP/GaAs HBT with high ruggedness for GSM power amplifiers

Enhancement-mode power heterojunction FET utilizing re-grown p/sup +/-GaAs gate with negligible off-state leakage current