Power semiconductor devices are key to delivering high-efficiency energy conversion in power electronics systems, which is critical in efforts to reduce energy loss, cut carbon dioxide emissions and create more sustainable technology. Although the use of wide or ultrawide-bandgap materials will be required to develop improved power devices, multidimensional architectures can also improve performance, regardless of the underlying material technology. In particular, multidimensional device architectures—such as superjunction, multi-channel and multi-gate technologies—can enable advances in the speed, efficiency and form factor of power electronics systems. Here we review the development of multidimensional device architectures for efficient power electronics. We explore the rationale for using multidimensional architectures and the different architectures available. We also consider the performance limits, scaling and material figure of merits of the architectures, and identify key technological challenges that need to be addressed to realize the full potential of the approach. This Review examines the use of multidimensional architectures—such as superjunction, multi-channel and multi-gate technologies—in power electronics devices, exploring the performance limits, scaling and material figure of merits of the different architectures. 

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Multidimensional device architectures for efficient power electronics

High-performance 2-D-electron-gas (2-DEG) channel and submicron fin-shaped channel have recently been demonstrated in vertical GaN power transistors. This indicates that, unlike Si and SiC, the inversion-type metal–oxide–semiconductor channel is no longer the “default option” for future GaN superjunction transistors. This paper demonstrates the design and simulation of GaN superjunction transistors with 2-DEG and fin channels, i.e., a superjunction current-aperture vertical electron transistor (SJ-CAVET) and a superjunction fin field-effect-transistor (SJ-FinFET). A breakdown voltage over 2.2 kV and a specific on-resistance ( $R_{\mathrm{\scriptscriptstyle ON},\mathrm {sp}}$ ) of $0.35~\text {m}\Omega \cdot \text {cm}^{2}$ were demonstrated in the simulated GaN SJ-CAVETs and SJ-FinFETs with 10- $\mu \text{m}$ -thick superjunction region. Mixed-mode simulations were used to evaluate their performance in 1.7 kV, 50-A power switching applications. Their $R_{\mathrm{\scriptscriptstyle ON},\mathrm {sp}}$ and die size are at least 30-to-50-fold smaller than that of today’s best 1.7-kV power transistors. Thanks to the smaller die size, the junction capacitances and switching charges are significantly smaller, allowing for a megahertz practical switching frequency which is at least tenfold higher than today’s 1.7-kV power transistors. The simulations of higher voltage GaN SJ-CAVETs and SJ-FinFETs up to 10 kV reveal consistent advantages over commercial transistors. These results show the great potentials of GaN SJ-CAVETs and SJ-FinFETs for future medium-voltage high-frequency power applications.

Design and Simulation of GaN Superjunction Transistors With 2-DEG Channels and Fin Channels

We have determined and evaluated the specific on-resistance (Ron,sp) vs breakdown voltage (BV) trade-off limits of vertical GaN-based conventional doped pn superjunction (SJ) and natural polarization superjunction (PSJ) devices using analytical models and numerical simulations. We have obtained much better performance on the vertical natural polarization superjunction devices based on the AlGaN/GaN and AlInN/GaN heterostructures instead of the conventional superjunction devices with alternating doped p/n pillars. Our results show that the drift-region Ron,sp of vertical GaN-based superjunction devices is one to more than four orders of magnitude lower than the 1D limit of GaN conventional unipolar devices at the same BV. For 1 and 10 kV devices, the optimized specific on-resistance of the drift region is about 10 and 300 times lower for conventional superjunction devices, but 1000 and 20 000 times lower for natural polarization superjunction devices.

Performance limits of vertical GaN of conventional doped pn and natural polarization superjunction devices

Recent progress in p-GaN trench-filling epitaxy has shown promise for the demonstration of GaN superjunction (SJ) devices. However, the presence of n-type interface charges at the regrowth interfaces has been widely observed. These interface charges pose great challenges to the design and performance evaluation of SJ devices. This work presents an analytical model for SJ devices with interface charges for the first time. In our model, two approaches are proposed to compensate interface charges, by the modulation of the SJ doping or the SJ geometry. Based on our model, an analytical study is conducted for GaN SJ transistors, revealing the design windows and optimal values of doping concentration and pillar width as a function of interface charge density. Finally, TCAD simulation is performed for vertical GaN SJ transistors, which validated our analytical model. Our results show that, with optimal designs, interface charges would only induce small degradation in the performance of GaN SJ devices. However, with the increased interface charge density, the design windows for pillar width and doping concentration become increasingly narrow and the upper limit in the pillar width window reduces quickly. When the interface charge density exceeds $\sim 3\times 10^{12}$ cm
 -2
, the design window of pillar width completely falls into the sub-micron range, indicating significant difficulties in fabrication. Vertical GaN SJ transistors with interface charges retain great advantages over conventional GaN power transistors, but have narrower design windows and require different design rules compared to ideal GaN SJ devices.

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Superjunction Power Transistors With Interface Charges: A Case Study for GaN

Franz-Keldysh effect in 4H-SiC p-n junction diodes under high electric field along the 〈11\bar{{\bf{2}}}0〉 direction

4H-SiC super junction, $0.63\ \mathrm{m}\Omega \text{cm}^{2}$ and 1170 V, V-groove trench MOSFETs (SJ-VMOSFET) were demonstrated. The specific on-resistance $(R_{\text{on},\text{sp}})$ of the SJ-VMOSFET is the lowest ever among all the reported SiC-MOSFETs with the blocking voltage $(B_{\mathrm{v}})$ over 600 V. Superior electrical properties were realized with the structural combination of the V-groove MOS channel and the charge balance at super junction area. The $R_{\text{on},\text{sp}}$ analysis of SJ-VMOSFET was carried out after mounted on a TO-268 5pin package having a Kelvin source terminal. The V-groove {033 8} channels could keep a high inversion mobility even in increasing doping concentration over $1\times 10^{18}$ cm−3. The excellent-static and -dynamic performances of SJ-VMOSFET were allowed to realize the ultra-low loss switching applications.

T. Kumazawa

Papers

$0.63\ \mathrm{m}\Omega \text{cm}^{2}$ / 1170 V 4H-SiC Super Junction V-Groove Trench MOSFET