PREFACE. ACKNOWLEDGMENTS. 1 INTRODUCTION. 1.1 Architecture of the Internet: Present and Future. 1.2 Router Architectures. 1.3 Commercial Core Router Examples. 1.4 Design of Core Routers. 1.5 IP Network Management. 1.6 Outline of the Book. 2 IP ADDRESS LOOKUP. 2.1 Overview. 2.2 Trie-Based Algorithms. 2.3 Hardware-Based Schemes. 2.4 IPv6 Lookup. 2.5 Comparison. 3 PACKET CLASSIFICATION. 3.1 Introduction. 3.2 Trie-Based Classifications. 3.3 Geometric Algorithms. 3.4 Heuristic Algorithms. 3.5 TCAM-Based Algorithms. 4 TRAFFIC MANAGEMENT. 4.1 Quality of Service. 4.2 Integrated Services. 4.3 Differentiated Services. 4.4 Traffic Policing and Shaping. 4.5 Packet Scheduling. 4.6 Buffer Management. 5 BASICS OF PACKET SWITCHING. 5.1 Fundamental Switching Concept. 5.2 Switch Fabric Classification. 5.3 Buffering Strategy in Switching Fabrics. 5.4 Multiplane Switching and Multistage Switching. 5.5 Performance of Basic Switches. 6 SHARED-MEMORY SWITCHES. 6.1 Linked List Approach. 6.2 Content Addressable Memory Approach. 6.3 Space-Time-Space Approach. 6.4 Scaling the Shared-Memory Switches. 6.5 Multicast Shared-Memory Switches. 7 INPUT-BUFFERED SWITCHES. 7.1 Scheduling in VOQ-Based Switches. 7.2 Maximum Matching. 7.3 Maximal Matching. 7.4 Randomized Matching Algorithms. 7.5 Frame-based Matching. 7.6 Stable Matching with Speedup. 8 BANYAN-BASED SWITCHES. 8.1 Banyan Networks. 8.2 Batcher-Sorting Network. 8.3 Output Contention Resolution Algorithms. 8.4 The Sunshine Switch. 8.5 Deflection Routing. 8.6 Multicast Copy Networks. 9 KNOCKOUT-BASED SWITCHES. 9.1 Single-Stage Knockout Switch. 9.2 Channel Grouping Principle. 9.3 Two-Stage Multicast Output-Buffered ATM Switch (MOBAS). 9.4 Appendix. 10 THE ABACUS SWITCH. 10.1 Basic Architecture. 10.2 Multicast Contention Resolution Algorithm. 10.3 Implementation of Input Port Controller. 10.4 Performance. 10.5 ATM Routing and Concentration (ARC) Chip. 10.6 Enhanced Abacus Switch. 10.7 Abacus Switch for Packet Switching. 11 CROSSPOINT BUFFERED SWITCHES. 11.1 Combined Input and Crosspoint Buffered Switches. 11.2 Combined Input and Crosspoint Buffered Switches with VOQ. 11.3 OCF-OCF: Oldest Cell First Scheduling. 11.4 LQF-RR: Longest Queue First and Round-Robin Scheduling in CIXB-1. 11.5 MCBF: Most Critical Buffer First Scheduling. 12 CLOS-NETWORK SWITCHES. 12.1 Routing Property of Clos Network Switches. 12.2 Looping Algorithm. 12.3 m-Matching Algorithm. 12.4 Euler Partition Algorithm. 12.5 Karol's Algorithm. 12.6 Frame-Based Matching Algorithm for Clos Network (f-MAC). 12.7 Concurrent Matching Algorithm for Clos Network (c-MAC). 12.8 Dual-Level Matching Algorithm for Clos Network (d-MAC). 12.9 The ATLANTA Switch. 12.10 Concurrent Round-Robin Dispatching (CRRD) Scheme. 12.11 The Path Switch. 13 MULTI-PLANE MULTI-STAGE BUFFERED SWITCH. 13.1 TrueWay Switch Architecture. 13.2 Packet Scheduling. 13.3 Stage-To-Stage Flow Control. 13.4 Port-To-Port Flow Control. 13.5 Performance Analysis. 13.6 Prototype. 14 LOAD-BALANCED SWITCHES. 14.1 Birkhoff-Von Neumann Switch. 14.2 Load-Balanced Birkhoff-von Neumann Switches. 14.3 Load-Balanced Birkhoff-von Neumann SwitchesWith FIFO Service. 15 OPTICAL PACKET SWITCHES. 15.1 Opto-Electronic Packet Switches. 15.2 Optoelectronic Packet Switch Case Study I. 15.3 Optoelectronic Packet Switch Case Study II. 15.4 All Optical Packet Switches. 15.5 Optical Packet Switch with Shared Fiber Delay Lines Single-stage Case. 15.6 All Optical Packet Switch with Shared Fiber Delay Lines - Three Stage Case. 16 HIGH-SPEED ROUTER CHIP SET. 16.1 Network Processors (NPs). 16.2 Co-Processors for Packet Classification. 16.3 Traffic Management Chips. 16.4 Switching Fabric Chips. INDEX.

High Performance Switches and Routers

For reasons of economy and flexibility, BISDN (Broadband Integrated Services Digital Network) is expected to replace existing application-oriented communication networks. ATM (Asynchronous Transfer Mode) is a high-speed packet-switching technique that has emerged as the most promising technology for BISDN. Since early 1980s, a large number of architectures have been proposed for ATM switching. In this paper, we present a descriptive survey of ATM switch architectures, with emphasis on electronic space-division point-to-point switches.

Survey of ATM switch architectures

Designing Least-Cost Nonblocking Broadband Networks

A system for controlling the flow of data cells through a packet switch combines both input and output buffers in a feedback loop. The fullness level of output buffers is continuously monitored and reported to an access device on the input side of the switch. The access device includes input buffers and a throttling device to stop the flow of data cells, and hold them in the input buffers, when the fullness level of the output buffers exceeds a predetermined level. A status message of output buffers fullness is compared to an access message indicating which output buffers are addressed by cells in the input buffers, and only those cells addressed to overfull output buffers are stopped by the throttling device.

Flow control system for packet switches

The asynchronous transfer mode (ATM) promises to be the ultimate on-premise internetworking technology. Its high-bandwidth uniform switches can transfer graphics, audio, video. and text from application to application at much higher speeds than now available. In fact, ATM may well be the technology that brings the computer and communications industries together. Because ATM as a public service offering by telecommunications companies will probably not be in place before 1996-1997, the authors focus on the ATM LAN and the corporate backbone. Most of the proposals on the internal architecture of the ATM switch are still at a research-and-evaluation stage, based on the switching architectures of the 1970s and 198Os. Various objectives, such as blocking, routing, performance and VLSI implementation, motivated past work. Although these attributes are essential, they don't address concerns important to the commercial ATM market, such as the general cost of ownership and incremental deployment, scalability, reliability, and efficient bandwidth utilization. The few ATM switches on the market today embody attributes that meet current demands but must evolve to meet the future. The authors assess the architectural characteristics deemed necessary for the ATM switch, providing an overview of its purpose and protocols, and summarize key ATM switch proposals. They summarize commercial market requirements and profile several commercially available systems to show the current gap between the research community and the commercial market, providing a model for the future. >

Finding the right ATM switch for the market

The authors propose a new space-division fast packet switch architecture based on banyan interconnection networks, called the tandem banyan switching fabric (TBSF). It consists of placing banyan networks in tandem, offering multiple paths from each input to each output, thus overcoming in a very simple way the effect of conflicts among packets (to which banyan networks are prone) and achieving output buffering. From a hardware implementation perspective, this architecture is simple in that it consists of several instances of only two VLSI chips, one implementing the banyan network and the other implementing the output buffer function. The basic structure and operation of the tandem banyan switching fabric are described, and its performance is discussed. The authors propose a modification to the basic structure which decreases the hardware complexity of the switch while maintaining its performance. An implementation of the banyan network using a high-performance BiCMOS sea-of-gates on 0.8- mu m technology is reported. >

T. Kwok

Papers

Architecture, performance, and implementation of the tandem banyan fast packet switch