This lecture note presents a new method to capture and represent compressible signals at a rate significantly below the Nyquist rate. This method, called compressive sensing, employs nonadaptive linear projections that preserve the structure of the signal; the signal is then reconstructed from these projections using an optimization process.

Compressive Sensing [Lecture Notes]

Design and implementation

Year 2009 marks the completion of 50 years of the invention of CORDIC (coordinate rotation digital computer) by Jack E. Volder. The beauty of CORDIC lies in the fact that by simple shift-add operations, it can perform several computing tasks such as the calculation of trigonometric, hyperbolic and logarithmic functions, real and complex multiplications, division, square-root, solution of linear systems, eigenvalue estimation, singular value decomposition, QR factorization and many others. As a consequence, CORDIC has been utilized for applications in diverse areas such as signal and image processing, communication systems, robotics and 3-D graphics apart from general scientific and technical computation. In this article, we present a brief overview of the key developments in the CORDIC algorithms and architectures along with their potential and upcoming applications.

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50 Years of CORDIC: Algorithms, Architectures, and Applications

In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

Programmable logic device including multipliers and configurations thereof to reduce resource utilization

A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform round-to-nearest and round-to-nearest-even operations. In addition, the bit position at which rounding occurs is preferably selectable. The specialized processing block preferably also includes saturation circuitry to prevent overflows and underflows, and the bit position at which saturation occurs also preferably is selectable. The selectability of both the rounding and saturation positions provides control of the output data word width. The rounding and saturation circuitry may be selectably located in different positions based on timing needs. Similarly, rounding may be speeded up using a look-ahead mode in which both rounded and unrounded results are computed in parallel, with the rounding logic selecting between those results.

Specialized processing block for programmable logic device

CORDIC is a versatile algorithm widely used for VLSI implementation of digital signal processing applications. This article presents a tutorial of how to use CORDIC to implement different communication subsystems that can be found in a software defined radio. Specifically, it shows how to use CORDIC to implement direct digital synthesizers, AM, PM, and FM analog modulators and ASK, PSK and FSK modulators, up-/down-converters of in-phase and quadrature signals, full mixers for complex signals, and phase detection for synchronizers. The article also shows some tricks to efficiently implement the algorithm

The use of CORDIC in software defined radios: a tutorial

A set of operators suitable for digit-serial FIR filtering is presented. The canonical and inverted forms are studied. In each of these structures both the symmetrical and anti-symmetrical particular cases are also covered. All circuits have been implemented using an EPF10K50 Altera FPGA. The main results show that the canonical form presents less occupation and higher throughput. The 8-tap filter versions implemented can be applied in real-time processing with sample rate ranging up to 7 MHz using the bit-serial versions and up to 25 MHz with the bit-parallel ones.

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A study about FPGA-based digital filters

This paper presents a course on digital signal processing with field-programmable gate arrays (FPGA) devices. The course integrates two separate disciplines, digital signal processing (DSP) and very large scale integration (VLSI) design, and focuses on the development of a sophisticated DSP design from simulation to fixed-point implementation. The structure and methodology used in the proposed course are oriented to the design and implementation of an fast Fourier transform (FFT) spectrum analyzer. This application covers most topics included in a DSP course and gives better results that those obtained with typical courses performing independent multiple simple experiments. The project is divided into modules that show specific learning necessities and determine the course contents and organization. Each laboratory part is dedicated to design and implements the block of the analyzer related to the theoretical content presented in the class. At the end of the course the students have designed all the pieces in the DSP project and have completed and verified the system. The used methodology enables students and engineers to understand and develop complex fixed-point applications, looking for the best signal processing algorithms on hardware implementations, and also results in more motivated and active students.

FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices

This paper proposes an efficient FPGA implementation of a common CORDIC architecture for circular and linear coordinates The proposed circuit is derived from the single coordinate CORDIC architectures and the mapping on the Xilinx slices is fully detailed Relative placed macros in VHDL have been designed to show the goodness of the proposed architecture All the circuits have been implemented in Virtex-E and Virtex-II devices and the results show that the area of the common architecture is hardly larger than the area of a single coordinate or single mode CORDIC architecture It is also shown that if a common architecture is modeled with RTL style its implementation requires the double of area and the maximum throughput decreases more than a half

Efficient FPGA implementation of Cordic algorithm for circular and linear coordinates

In this paper the design of a family of digit-serial 8th-order FIR filters with programmable coefficients is presented. Both input data and coefficient size are 8 bits, but every filter of the family allows the computation with full precision of the intermediate data. The output data is truncated to 8 bits. The design of both, the digit-serial multiple precision multiply-and-accumulate and the digit-serial multiple-to-single precision converter, is detailed. All filters were implemented using an ALTERA FPGA being useful in applications with sample rate range from 5 to 22 MHz.

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T. Sansaloni

Papers

The use of CORDIC in software defined radios: a tutorial

A study about FPGA-based digital filters

FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices

Efficient FPGA implementation of Cordic algorithm for circular and linear coordinates

Design and FPGA implementation of digit-serial FIR filters