A method of determining the effect of the degradation of MOSFET on the frequency of a Ring Oscillator (RO) consisting of an odd prime number of inverter stages, each of the inverters stages having an NMOS and a PMOS field-effect transistor is described. The method includes the steps of: a) selecting one inverter from the inverter stages of the RO, the selected inverter having testable nodes, the testable nodes being connected to inputs and outputs of the NMOS and a PMOS field-effect transistors (FET) forming the selected inverter; b) simultaneously stressing under a set of stress conditions 1) all of the NMOS FETs of each of the inverter stages, 2) all of the PMOS FETs, and 3) all of the NMOS FETs and PMOS FETs in the RO; c) measuring a shift in selected device parameters in the selected inverter; d) measuring a frequency degradation of the entire RO; and e) establishing a relationship between the shift in the device parameters and the frequency degradation and relating the relationship to a known degradation mechanism Furthermore, on-chip pass gates controlled by appropriate off-chip DC voltage signals, allow parallel DC stressing, as well as forcing an off-chip AC voltage waveform to a given MOSFET type device (either PMOSFET or NMOSFET) on every inverter stage of the RO. The RO circuit makes it possible to investigate the effect on the RO frequency degradation, caused by any DC MOSFET degradation mechanism as well as by any external AC voltage waveform known to be representative of a critical circuit operation. Thus, the dependence of the RO frequency on device degradation mechanisms activated during a critical circuit operation can be carefully investigated and quantified.

Ring oscillator design for MOSFET device reliability investigations and its use for in-line monitoring

A voltage controlled ring oscillator (VCRO) that can operate at low voltage and provide a variable periodic output. A plurality of transistors form a ring oscillator and a selected transistor in the ring oscillator has a body which can float with respect to ground potential. The selected transistor has a threshold voltage which is controllable by a voltage applied to the transistor body. A control input is coupled to the transistor body such that the body of the transistor can be charged by the control input. Charging the body alters the threshold voltage of the transistor and thereby controls the oscillation frequency of the oscillator.

Voltage controlled oscillator utilizing threshold voltage control of silicon on insulator MOSFETS

A charge pump method and apparatus is described having various aspects. Noise injection from a charge pump to other circuits may be reduced by limiting both positive and negative clock transition rates, as well as by limiting drive currents within clock generator driver circuits, and also by increasing a control node AC impedance of certain transfer capacitor coupling switches. A single-phase clock may be used to control as many as all active switches within a charge pump, and capacitive coupling may simplify biasing and timing for clock signals controlling transfer capacitor coupling switches. Any combination of such aspects of the method or apparatus may be employed to quiet and/or simplify charge pump designs over a wide range of charge pump architectures.

Low noise charge pump method and apparatus

Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.

Low-noise high efficiency bias generation circuits and method

A method and system of voltage compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of voltage compensation.

Voltage compensated integrated circuits

A ring oscillator comprising an odd number of inverters connected in a ring, and apparatus for driving the ring oscillator so that it oscillates at a frequency slightly less than its maximum oscillating frequency such that harmonics of the oscillating frequency are suppressed.

Ring oscillator having a substantially sinusoidal signal

A ring oscillator comprising: a plurality of sub-feedback loops, each comprising a pair of serially connected inverters and a feedback inverter having its input coupled to the output of the pair of inverters and its output connected to the input of the pair of inverters, the pairs of inverters being connected in a ring, and a downstream inverter of each respective pair of inverters forming an upstream inverter of an immediately following pair of inverters.

High speed wide tuning range multi-phase output ring oscillator

A method of phase detecting a data input NRZ signal comprises applying the input data signal to a pair of parallel channels each comprising the same phase delay, and each clocked using the same clock signal. The phase delayed input data signal is coupled to respective inputs of a pair of phase comparators. The input data signal is coupled to a further channel comprising the same phase delay, and the further channel is clocked using the same clock signal. The phase delayed input signal is passed from the further channel through a further delay which is a fraction of that same phase delay, and the further delay is clocked using the clock signal. The further delayed input data signal is applied to another input of one of the phase comparators. The input data signal is applied through another phase delay which has the fraction of the aforenoted same phase delay (but is unclocked), to another input of the other of the phase comparators. Output signals are obtained from each of the phase comparators.

Tadeusz Kwasniewski

Papers

Ring oscillator having a substantially sinusoidal signal

High speed wide tuning range multi-phase output ring oscillator

Pipelined phase detector for clock recovery