In this paper, a new topology for cascaded multilevel converter based on submultilevel converter units and full-bridge converters is proposed. The proposed topology significantly reduces the number of dc voltage sources, switches, IGBTs, and power diodes as the number of output voltage levels increases. Also, an algorithm to determine dc voltage sources magnitudes is proposed. To synthesize maximum levels at the output voltage, the proposed topology is optimized for various objectives, such as the minimization of the number of switches, gate driver circuits and capacitors, and blocking voltage on switches. The analytical analyses of the power losses of the proposed converter are also presented. The operation and performance of the proposed multilevel converter have been evaluated with the experimental results of a single-phase 125-level prototype converter.

A New Multilevel Converter Topology With Reduced Number of Power Electronic Components

In this paper, a novel current control approach called model predictive direct current control (MPDCC) is presented. The controller takes into account the discrete states of the voltage source inverter (VSI), and the current errors are predicted for each sampling period. Voltage vectors are selected by a graph algorithm, whereby the most appropriate vector is chosen based on an optimization criterion. However, this depends on whether the state of the system is transient or steady. In the first case, the current error should be minimized as fast as possible in order to obtain fast dynamics. In the latter one, the VSI switching behavior is optimized since the switching losses account for a large amount of the total converter losses in high-power drive systems. MPDCC has been developed for a general neutral-point isolated resistive-inductive load with an internal voltage source. For demonstration, the presented control strategy has been implemented on a small-scale permanent-magnet synchronous machine drive system with a two-level VSI. This new approach has several advantages. The most important one is that the switching frequency is reduced up to 70% compared to linear control combined with pulsewidth modulation. Second, MPDCC obtains fast dynamic responses, which are already known from, e.g., direct torque control.

Switching Frequency Reduction Using Model Predictive Direct Current Control for High-Power Voltage Source Inverters

This paper presents a comparison of three topologies of multilevel inverters applied to drive an induction motor of 500 kVA/4.16 kV rating. The multilevel inverters analyzed are the following: a neutral-point-clamped inverter, a symmetrical cascaded multilevel inverter, and a hybrid asymmetrical cascaded multilevel inverter. The performance indexes used in the comparison are total harmonic distortion, first-order distortion factor, second-order distortion factor, common-mode voltage, semiconductor power loss distribution, and heat-sink volume. The multilevel inverters are designed to present 99% efficiency at the nominal operating point, and the aforementioned performance indexes are compared for distinct values of amplitude modulation depth.

Comparison of Neutral-Point-Clamped, Symmetrical, and Hybrid Asymmetrical Multilevel Inverters

The design optimization of H5, H6, neutral point clamped, active-neutral point clamped, and conergy-NPC transformerless photovoltaic (PV) inverters is presented in this paper. The components reliability in terms of the corresponding malfunctions, affecting the PV inverter maintenance cost during the operational lifetime period of the PV installation, is also considered in the optimization process. According to the results of the proposed design method, different optimal values of the PV inverter design variables are derived for each PV inverter topology and installation site. The H5, H6, neutral point clamped, active-neutral point clamped and conergy-NPC PV inverters designed using the proposed optimization process feature lower levelized cost of generated electricity and lifetime cost, longer mean time between failures and inject more PV-generated energy into the electric grid than their nonoptimized counterparts, thus maximizing the total economic benefit obtained during the operational time of the PV system.

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Optimal Design of Modern Transformerless PV Inverter Topologies

In this paper, a novel four-level inverter will be presented and analyzed. The proposed inverter topology, which is composed of a conventional two-level and a three-level neutral-point clamped (NPC) inverter, is suitable for high-voltage and high-power applications. The proposed inverter, when it is compared with the conventional four-level NPC pulsewidth modulation inverter, exhibits the following advantages: a) ability of changing the power losses distribution profile among the devices by selecting a suitable switching strategy; b) reduction of total inverter power semiconductor device losses; c) ability of bidirectional operation for all power semiconductor switches; and d) easy implementation using existing power semiconductor modules. The effect of conduction and switching losses profiles of the proposed inverter for different switching strategies is examined under different loads, power factors, and modulation indices. The dc-link capacitors voltages are effectively balanced via a proposed self-voltage balancing topology, without the need of isolated dc voltage sources or additional voltage stabilizing circuits. Finally, the theoretical results are confirmed by simulation and experimental results

A Novel Four-Level Voltage Source Inverter—Influence of Switching Strategies on the Distribution of Power Losses

The multi-level inverter system is very promising in AC drives, when both reduced harmonic content and high power are required. But, as the output voltage level increase, the number of using the semiconductor device is increased. In case of multi-level inverter system, the loss of semiconductor devices cannot be analyzed by conventional methods. The reason is that the loss of each the semiconductor device is different from one another unlike 2-level and the diode clamped inverter system needs extra clamping diode. In this paper, a simple and accurate method of computing conduction and switching loss is proposed for multi-level inverter system. The validity of the proposed method is proven for 3-level and 4-level diode clamped inverter system.

Tae-Jin Kim

Papers

The analysis of conduction and switching losses in multi-level inverter system