In a system and method for accessing messages in a data store in a gateway, a data frame request, which is a structured SQL query, is received at the gateway. The received data frame request is applied to the gateway data store, which stores messages. A data frame is generated that comprises messages from the data store that are responsive to the received data frame request, the data frame having a format that is readable by a character editor.

System and method for exchanging information among exchange applications

This is invention comprises a method an apparatus for Infinite Network Packet Capture System (INPCS). The INPCS is a high performance data capture recorder capable of capturing and archiving all network traffic present on a single network or multiple networks. This device can be attached to Ethernet networks via copper or SX fiber via either a SPAN port (101) router configuration or via an optical splitter (102). By this method, multiple sources or network traffic including gigabit Ethernet switches (102) may provide parallelized data feeds to the capture appliance (104), effectively increasing collective data capture capacity. Multiple captured streams are merged into a consolidated time indexed capture stream to support asymmetrically routed network traffic as well as other merged streams for external consumption.

Method and apparatus for network packet capture distributed storage system

An encryption technique is disclosed for encrypting a plurality of data blocks of a data segment where the encryption selectively switches between a blockwise independent randomized (BIR) encryption mode and a cipher block chaining (CBC) encryption mode based on a configurable feedback stride. A corresponding decryption technique is also disclosed.

Method and System for High Throughput Blockwise Independent Encryption/Decryption

A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Flexible architecture and instruction for advanced encryption standard (AES)

An address to access a location in a storage device (106, 204) is received, and the address is scrambled. Write data is encrypted using an encryption key. The encrypted write data is stored in the storage device at a location of the storage device specified by the scrambled address.

Scrambling An Address And Encrypting Write Data For Storing In A Storage Device

The encryption/decryption device includes: a data structure analysis block for receiving encrypted data or data to be encrypted and outputting control data and also the encrypted data or the data to be encrypted as processing block input data; a data control block for determining a mode selection signal according to the control data; and a shared processing block for performing encryption or decryption for the processing block input data and outputting the result. The shared processing block is configured to have the ability to perform encryption and decryption in either of the CBC mode and the CFB mode by performing ECB processing using input key data, and performs encryption or decryption in the mode indicated by the mode selection signal.

Encrypting/decrypting device and method, encrypting device and method, decrypting device and method, and transmitting/receiving device

An interface block (11) converts the format of input downstream data (STRM). A CPU (12) receives the format-converted data (DIF) and realizes the MAC function. A TEK process block (13) receives TEK process data (DTEK) obtained from the data (DIF), analyzes the data structure of the TEK process data, and performs decryption processing based on a result of the analysis.

Digital two-way communication control device and its method

Encryption/decryption device and method, encryption device and method, decryption device and method, and transmission/reception apparatus

An interface block ( 11 ) converts the format of input downstream data (STRM). A CPU ( 12 ) receives the format-converted data (DIF) and realizes the MAC function. A TEK process block ( 13 ) receives TEK process data (DTEK) obtained from the data (DIF), analyzes the data structure of the TEK process data, and performs decryption processing based on a result of the analysis.

Device and method for controlling digital bidirectional communication

In an error and sync detection circuit, 7-bit byte data is rearranged by a data rearrangement block into 8-bit byte data where 1 byte is comprised of 8 bits. Thereafter, the 8-bit byte data is consistently used throughout the process, and each of such byte data is stored in a data storage block, which is a RAM. In a parity check block, a sync detection operation and a parity check operation are performed on the byte data from the data rearrangement block and the byte data from the data storage block, which has been delayed by 1496 clocks. Thus, the byte-to-byte conversion process eliminates the need for a parallel-to-serial conversion circuit and a serial-to-parallel conversion circuit. Use of a RAM for storing the byte data eliminates the need for a 1496-stage delay element.

Taemi Wada

Papers

Encrypting/decrypting device and method, encrypting device and method, decrypting device and method, and transmitting/receiving device

Digital two-way communication control device and its method

Encryption/decryption device and method, encryption device and method, decryption device and method, and transmission/reception apparatus

Device and method for controlling digital bidirectional communication

Device and method for error and sync detection