An intelligent well system and method has a sand face completion and a monitoring system to monitor application of a well operation. Various equipment and services may be used. In another aspect, the invention provides a monitoring system for determining placement of a well treatment. Yet another aspect of the invention is an instrumented sand screen. Another aspect is a connector for routing control lines.

Intelligent well system and method

A well system utilizes a control line system. The control line system is implemented with a completion of the type deployed in a wellbore. The control line system facilitates transmission of monitoring, command or other types of control and telemetry. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Well communication system

A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal.

Dual loop architecture useful for a programmable clock source and clock multiplier applications

A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.

Multi-frequency clock synthesizer

Temperature compensation is achieved by adjusting a divide ratio of a multi-modulus divider circuit in a feedback path of a phase-locked loop based on the detected temperature. The divide ratio is adjusted based on stored adjustment values stored in non-volatile memory. Interpolation may be used to interpolate between the stored adjustment values.

Method and apparatus for temperature compensation

A fractional frequency divider ( 28 ) includes a latch ( 31 ) for holding frequency division data, a ΔΣ modulator ( 33 ), a digital dither circuit ( 32 ) for receiving a digital input F representing fraction part of the frequency division data from the latch ( 31 ) and supplying a digital output alternately changing between F+k and F−k (where k is an integer) or a F value itself to the ΔΣ modulator ( 33 ), and circuit means ( 34 through 38 ) for executing fractional frequency division based on integer part (M value) of the frequency division data and an output of the ΔΣ modulator ( 33 ). The digital dither circuit ( 32 ) is useful for suppressing a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the ΔΣ modulator ( 33 ) receives a particular F value (e.g., F=2 n−1 ).

Signal processing device, signal processing method, delta-sigma modulation type fractional division pll frequency synthesizer, radio communication device, delta-sigma modulation type d/a converter

A temperature compensating crystal oscillation device includes a constant voltage circuit (12) for outputting a predetermined voltage independent of the ambient temperature, a temperature sensor circuit (13) for outputting a voltage in proportion to the ambient temperature, and a control circuit (14) for receiving the constant voltage output from the constant voltage circuit (12) and the voltage output in proportion to the temperature from the temperature sensor circuit (13) and for generating a control voltage (Vc) used for compensating a temperature characteristic of a quartz oscillator in the entire range of the ambient temperature through polygonal lines approximation of a negative cubic curve by using continuous lines. Furthermore, the crystal oscillation device includes a VCXO (15) whose oscillation frequency is controlled to be a predetermined value by the control voltage (Vc), and a ROM/RAM circuit (16) for storing temperature compensating parameters used for compensation of a temperature characteristic of the control voltage (Vc) for optimizing the oscillation frequency of the VCXO (15).

Function generator, crystal oscillation device and method of adjusting crystal oscillation device

It is possible to obtain a low spurious of a delta-sigma type fraction division PLL synthesizer. The delta-sigma type fraction division PLL synthesizer includes a first and a second L-value accumulator (31, 30), and an adder (29) for calculating a difference of overflow signals (16, 17) of the first and the second L-value accumulator (31, 30), so that the output of the adder (29) switches the division ratio of a variable divider (2) having a division ratio which can be switched to M, M+1, M-1. Thus, frequency of spurious generated by an operation noise of the first and the second L-value accumulator (31, 30) is shifted to a higher frequency component than the prior art and removed by a loop filter (low pass filter) (5).

Delta-sigma type fraction division pll synthesizer

A crystal oscillation device with a temperature compensation function comprising: a constant voltage circuit (12) for outputting a predetermined voltage that does not depend on the ambient temperature; a temperature sensor circuit (13) for outputting a voltage proportional to the ambient temperature; and a control circuit (14) for generating a control voltage (Vc) which receives a constant voltage output of the constant voltage circuit (12) and a voltage output of the temperature sensor circuit (13) proportional to temperature and which performs polygonal line approximation, by using a continuous line, of a negative cubic curve for compensating for the temperature characteristic of a crystal oscillator over the entire range of the ambient temperature. The crystal oscillation device further includes a VCXO (15) whose oscillation frequency is controlled to a predetermined value by the control voltage (Vc), and a ROM/RAM circuit (16) where a temperature compensation parameter for compensating for the temperature characteristic of the control voltage (Vc) which is outputted by the control circuit (14) and used to optimize the oscillation frequency outputted by the VCXO (15) is stored.

Function generation circuit, crystal oscillation device, and method of adjusting the crystal oscillation device

An automatic gain control device includes amplifiers cascaded, each having a variable gain; level measurement portions respectively corresponding to the amplifiers, where each of the level measurement portions measures a level of an output signal of a corresponding one of the amplifiers in a level measurement period indicated by a level measurement signal; error calculators respectively corresponding to the level measurement portions, where each of the error calculators compares a level measured by a corresponding one of the level measurement portions with a threshold which is set so that a corresponding one of the amplifiers will not saturate, and outputs a comparison result as an error signal; a gain computation section which updates one of the gains of the amplifiers at a time corresponding to a gain update signal, based on the error signals; and an operation controller which generates the level measurement signal and the gain update signal.

Takaharu Saeki

Papers

Signal processing device, signal processing method, delta-sigma modulation type fractional division pll frequency synthesizer, radio communication device, delta-sigma modulation type d/a converter

Function generator, crystal oscillation device and method of adjusting crystal oscillation device

Delta-sigma type fraction division pll synthesizer

Function generation circuit, crystal oscillation device, and method of adjusting the crystal oscillation device

Automatic gain control device and electronic device