The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Semiconductor Integrated Circuit Device

The disclosed invention is intended to decrease the power consumption of a pulse latch circuit. A pulse latch circuit that operates in sync with a pulsed clock signal, including a first operation mode in which shifting test pattern scan data is performed and a second operation mode in which shifting the test pattern scan data is not performed, comprises the following circuits: a first latch circuit that is able to latch input data in sync with the clock signal; a second latch circuit that is connected to the first latch circuit and is able to latch the test pattern scan data to be shifted in sync with the clock signal; and a control circuit that stops supply of the clock signal to the second latch circuit during the second operation mode. By thus stopping the supply of the clock signal to the second latch circuit, decrease the power consumption is achieved.

Pulse latch circuit and semiconductor integrated circuit

The circuit forms an edge-triggered D-Flip-Flop with a master/slave configuration. The master circuit has only one master switch controlled by a clock signal and followed by a first inverter. The slave circuit has a slave switch followed by a second inverter and a regenerative feedback-loop. The master and slave switches can easily be realized using n-MOS-transistors instead of transmission gates, thus achieving small chip area. The Flip-Flop can easily be amended by set and reset devices and it is suitable for mass applications such as memory and microprocessor chips.

Edge-triggered d-flip-flop circuit

PROBLEM TO BE SOLVED: To provide a latch circuit that operates at high speed with a low voltage, and so on. SOLUTION: The present invention comprises a transmission gate 5, an inverter circuit 6, a capacitor C2 for storing data, and a clocked inverter circuit 9. A threshold voltage of an MOS transistor comprising the transmission gate 5 is made relatively higher than that of an MOS transistor comprising the clocked inverter circuit 9. When a clock signal CK is in an H level, the transmission gate 5 is turned on to pass input data, stored data in the capacitor C2 are updated, the inverter circuit 6 inverts out the updated data, and the clocked inverter circuit 9 is turned on to invert out the input data. When the clock signal CK is in an L level on the other hand, the transmission gate 5 is turned off, the capacitor C2 holds the stored data, the inverter circuit 6 inverts out the stored data, and the clocked inverter circuit 9 stops outputting. COPYRIGHT: (C)2006,JPO&NCIPI

Latch circuit and flip-flop circuit

The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit Clock signals whose phases are inverted from each other are input to gates of the first and second transistors Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit

Storage Circuit and Semiconductor Device

PROBLEM TO BE SOLVED: To operate a flip-flop circuit at high speed which is the important component of a semiconductor integrated circuit and to reduce the space required. SOLUTION: A first latch circuit 1 for fetching data is of dynamic type, a second latch circuit 2 for storing, holding and outputting the data is of a static type. Both circuits 1 and 2 are connected serially and connected through a buffer circuit 14 to an output terminal Q. A switch control circuit 15 receiving a clock CK complementarily operates a first switch circuit 11 and a second switch circuit 12. A capacitor Cm parasitic to a node A holds a signal D only in the OFF period of a switch 11, shifts it to a second storage circuit 13 at the fall of the CK and statically holds it. The second storage circuit 13 is composed of an inverter and a clocked inverter for instance and constitutes a positive feedback loop by control from the switch control circuit 15.

Takahashi Fumikazu

Papers

Flip-flop circuit