A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to “a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.

Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit

A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

Semiconductor reliability test chip

In a hierarchical VLSI layout design, the block-level layout design is called a "chip floor plan" In this paper, a semi-automatic VLSI chip floor plan algorithm and its implementation are presented The initial block placement is obtained by an attractive and repulsive force method (AR method), and the subsequent block packing process is performed by gradually moving and reshaping blocks with chip boundary shrinking The chip area estimation is performed by using individual block area calculations from empirically obtained equations A set of interactive commands is also provided to facilitate the manual optimization processes using a color graphic terminal By processing several practical VLSI circuits, it is shown that the method is very effective for handling various kinds of blocks and is able to reduce the design effort required to achieve the chip floor plan

CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design

In the traditional approach to channel routing, terminals must be located on grid points and wire segments must be placed on grid lines. Without using the grids, we can take advantage of the two interconnection layers with variable wire width and spacing. Terminals are no longer required to be on grids, and nets may even have different wire widths. The new gridless approach which we propose is based on design rules. The objective is to minimize the routing area, while keeping the constraints of wire widths and spacing satisfied. This router is also capable of handling channels with irregular boundaries, and cyclic constraints. The algorithm has been implemented in C language, and will be integrated into our BBL (Berkeley Building-Block Layout) system.

Glitter: A Gridless Variable-Width Channel Router

In the traditional approach to channel routing, terminals must be located ogrid points and wire segments must be placed on grid lines. Without using the grids, we can take advantage of the two interconnection layers with variable wire width and spacing. Termi­ nals are no longer required to be on grids, and nets may even have different wire widths. The new gridless approach which we propose is based on design rules. The objective is to minimize the routing area, while keeping the constraints of wire widths and spacing satisfied. This router is also capable of handling channels with irregular boundaries, and cyclic constraints. The algorithm has been implemented in C lan­ guage, and will be integrated into our BBL (Berkeley Building-Block Layout) system.

Glitter: A Gridless V ariable- Width Channel Router

A "grid-free" channel router (termed GFR) is reported. GFR does not employ grid lines and can obtain better results than the fixed-grid method. Additionally, GFR has several optional functions, such as "constraint loop breaking", "total branch length minimization", "constraint chain cutting" and "layer changing". The algorithms of these functions are outlined and results obtained by using them are presented.

A "Grid-free" Channel Router

A simple-model routing program -MIRAGE- which is used in the hierarchical layout design of large scale IC masks is described together with some experimental results. By applying it hierarchically several times, satisfactory results can generally be obtained.

MIRAGE - A Simple-Model Routing Program for the Hierarchical Layout Design of IC Masks

An object of the present invention is to obtain a gate array type semiconductor integrated circuit device in which wiring restrictions upon separate basic cells are relaxed so as to relatively easily provide wirings among the basic cells. A gate array type semiconductor integrated circuit is configured in the conditions that a lateral length of each of connection pins (25) of basic cells (1) is determined as one-wiring pitch (W1) and that a distance between the connection pins (25) of adjacent ones of the basic cells in any of cell alignments (3) is determined as the one-wiring pitch (W1). Since two or more longitudinal wirings can be formed extending from each of the connection pins of the basic cells in a second direction, the wirings among the basic cells can be provided relatively easily.

Semiconductor integrated circuit having lengthened connection pins for connection to external wirings

A standard-cell-based layout system for MOS-LSI termed MILD is reported. MILD has several features which seem to be profitable from the practical viewpoint of LSI developers; one of them is that macro blocks such as memory cells can be contained in the chip laid out.

Takao Nagai

Papers

A "Grid-free" Channel Router

MIRAGE - A Simple-Model Routing Program for the Hierarchical Layout Design of IC Masks

Semiconductor integrated circuit having lengthened connection pins for connection to external wirings

MILD - A Cell-Based Layout System for MOS-LSI