Activities performed in organizations are coordinated via communication between the people involved The sentences used to communicate are naturally structured by subject, verb, and object The subject describes the actor, the verb the action and the object what is affected by the action Subject-oriented Business Process Management (S-BPM) as presented in this book is based on this simple structure which enables process-oriented thinking and process modeling S-BPM puts the subject of a process at the center of attention and thus deals with business processes and their organizational environment from a new perspective, meeting organizational requirements in a much better way than traditional approaches Subjects represent agents of an action in a process, which can be either technical or human (eg a thread in an IT system or a clerk) A process structures the actions of each subject and coordinates the required communication among the subjects S-BPM provides a coherent procedural framework to model and analyze business processes: its focus is the cooperation of all stakeholders involved in the strategic, tactical, and operational issues, sharing their knowledge in a networked structure The authors illustrate how each modeling activity through the whole development lifecycle can be supported through the use of appropriate software tools The presentation style focuses on professionals in industry, and on students specializing in process management or organizational modeling Each chapter begins with a summary of key findings and is full of examples, hints, and possible pitfalls An interpreter model, a toolbox, and a glossary summarizing the main terms complete the book The web site wwwi2pmnet provides additional software tools and further material

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Subject-Oriented Business Process Management

A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Semiconductor integrated circuit device having power reduction mechanism

In one embodiment to the invention, a semiconductor circuit includes a substrate and a first well formed in the substrate. A first group of field effect transistors is formed in the first well and has a first body. The circuit includes a first body voltage to the first body to forward body bias the first group of field effect transistors. The circuit includes a first isolation structure to contain the first body voltage in the first well. In another embodiment, the circuit further includes a second group of field effect transistors having a non-forward body bias and the first isolation structure prevents the first body voltage from influencing a voltage of a body of the second group of field effect transistors. In yet another embodiment, a second isolation structure adjacent to the second well contain a second body voltage in a second well holding the second group of field effect transistors.

Multiple well transistor circuits having forward body bias

In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.

Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device

The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Semiconductor Integrated Circuit Device

The semiconductor IC according to this invention comprises an internal circuit including a plurality of transistors formed on a P-type or an N-type substrate (or a well) which carries out a prescribed signal processing operation during the time of operation mode, a standby detection circuit which generates a standby detection signal of active level by detecting standby mode, a bias potential generating circuit which generates a forward bias potential from the substrate (well) of the transistor to the source electrode, and a switching circuit which supplies to the substrate (well) the potential of the source electrode and the bias potential in response to the active level and the inactive level, respectively, of the standby detection signal. At the time of the operation mode, a high speed operation is secured by bringing the transistors to a low threshold voltage by receiving the supply of the bias potential, while at the time of the standby mode, the generation of malfunctions and defective data holding are prevented and the power consumption is saved by raising the threshold voltage of the transistors through a halt of supply of the bias voltage to the substrate (well).

Semiconductor integrated circuit incorporated with substrate bias control circuit

In a semiconductor integrated circuit device, a MOS transistor has a relatively high built-in threshold, and in operation, a substrate bias is applied to the MOS transistor so as to cause the MOS transistor to forcibly have a reduced threshold, so that the MOS transistor operates at a high speed with the reduced threshold. When noise is detected, application of the substrate bias is stopped so that the MOS transistor restores the relatively high built-in threshold, and simultaneously, the MOS transistor is put in a standby condition, so that a malfunction can be prevented with the relatively high built-in threshold.

Semiconductor integrated circuit which prevents malfunctions caused by noise

It is not that difficult to visualize business processes as a model and execute them using today’s BPMS products. However, it is difficult for a worker at a work site to simply and clearly model processes to be executed, and then express with certainty the business scenario within the entire company’s activities to which those processes are related. In addition, a shorter cycle for continuous BPM improvement activity is strongly desired, where the model is improved from results gathered as processes based on that model are executed. The "CGAA/EES development methodology" developed by NEC provides an overall optimization solution that overcomes these issues by bringing a top-down approach to subject-oriented BPM.

CGAA/EES at NEC Corporation, Powered by S-BPM: The Subject-Oriented BPM Development Technique Using Top-Down Approach

PURPOSE:To prevent a malfunction due to a noise generated in a GND line or a VDD line for a semiconductor integrated circuit device constituted of a MOS transistor which has been made minute and whose threshold value is low CONSTITUTION:In an ordinary operation, a MOS transistor 110 which has been formed at a high threshold voltage is changed into a low threshold voltage by a substrate bias 106, and it is operated at high speed The application of the substrate bias is suspended by a noise-level identification circuit 101 which detects a noise or a sudden change in a power supply voltage, at the same time, a circuit is changed to a standby state, the generation of a malfunction is prevented, the application of the substrate bias is resumed when a change in the noise or the sudden change in the level of the power supply voltage is stopped, the standby state is released, so that the circuit operation continues operating

Takeshi Hirayama

Papers

Semiconductor integrated circuit incorporated with substrate bias control circuit

Semiconductor integrated circuit which prevents malfunctions caused by noise

CGAA/EES at NEC Corporation, Powered by S-BPM: The Subject-Oriented BPM Development Technique Using Top-Down Approach

Semiconductor integrated circuit device