In a previous work it was argued that by studying evolved designs of gradually increasing scale, one might be able to discern new, efficient, and generalisable principles of design. These ideas are tested in the context of designing digital circuits, particularly arithmetic circuits. This process of discovery is seen as a principle extraction loop in which the evolved data is analysed both phenotypically and genotypically by processes of data mining and landscape analysis. The information extracted is then fed back into the evolutionary algorithm to enhance its search capabilities and hence increase the likelihood of identifying new principles which explain how to build systems which are too large to evolve.

Principles in the Evolutionary Design of Digital Circuits—Part II

In contrast to conventional hardware where the structure is irreversibly fixed in the design process, evolvable hardware (EHW) is designed to adapt to changes in task requirements or changes in the environment, through its ability to reconfigure its own hardware structure dynamically and autonomously. This capacity for adaptation, achieved by employing efficient search algorithms based on the metaphor of evolution, has great potential for the development of innovative industrial applications. This paper introduces EHW chips and six applications currently being developed as part of MITI's Real-World Computing Project; an analog EHW chip for cellular phones, a clock-timing architecture for Giga hertz systems, a neural network EHW chip capable of autonomous reconfiguration, a data compression EHW chip for electrophotographic printers, and a gate-level EHW chip for use in prosthetic hands and robot navigation.

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Real-world applications of analog and digital evolvable hardware

The paper studies the role of neutrality in the fitness landscapes associated with the evolutionary design of digital circuits and particularly the three-bit binary multiplier. For the purpose of the study, digital circuits are evolved extrinsically on an array of logic cells. To evolve on an array of cells, a genotype-phenotype mapping has been devised by which neutrality can be embedded in the resulting fitness landscape. It is argued that landscape neutrality is beneficial for digital circuit evolution.

The Advantages of Landscape Neutrality in Digital Circuit Evolution

For many evolvable hardware applications, small size and power efficiency are critical design considerations. One manner in which significant memory, and thus, power and space savings can be realized in a hardware-based evolutionary algorithm is to represent populations of candidate solutions as probability vectors rather than as sets of bit strings. The compact genetic algorithm (CGA) is a probability vector-based evolutionary algorithm that can be efficiently and elegantly implemented in digital hardware. Unfortunately, the CGA is a very weak, first order, evolutionary algorithm that is unlikely to possess sufficient search power to enable intrinsic evolvable hardware applications. In this paper, we further develop a number of modifications to the basic CGA that significantly improve its search efficacy without substantially increasing the size and complexity of its hardware implementation. The paper provides both benchmark results demonstrating increased efficacy and a conceptual data path/microcontroller design suitable for implementation in digital hardware. Following, it demonstrates efficient implementation by making a head-to-head comparison of field programmable gate array implementations of both the classic CGA and a member of our family of modifications. The paper concludes with a discussion of future research, including several additional extensions that we expect will further increase search efficacy without increasing implementation cost.

A family of compact genetic algorithms for intrinsic evolvable hardware

We propose a hardware implementation of the Compact Genetic Algorithm (GA). The design is realized using the Verilog hardware description language (HDL) and then fabricated on an FPGA. Our design, though simple, runs about 1000 times faster than the software executing on a workstation. An alternative hardware for linkage learning is also proposed in order to enhance the capability of the Compact GA to solve highly deceptive problems.

A hardware implementation of the Compact Genetic Algorithm

The advantage of Evolvable Hardware (EHW) over traditional hardware is its capacity for dynamic and autonomous adaptation, which is achieved through by Genetic Algorithms (GAs). In most EHW implementations, these GAs are executed by software on a personal computer (PC) or workstation (WS). However, as a wider variety of applications come to utilize EHW, this is not always practical. One solution is to have the GA operations carried out by the hardware itself, by integrating these together with reconfigurable hardware logic like PLA (Programmble Logic Array) or FPGA (Field Programmable Gate Array) on to a single LSI chip. A compact and quickly reconfigurable EHW chip like this could service as an off-the-shelf device for practical applications that require on-line hardware reconfiguration. In this paper, we describe an integrated EHW LSI chip that consists of GA hardware, reconfigurable hardware logic, a chromosome memory, a training data memory, and a 16-bit CPU core (NEC V30). An application of this chip is also described in a myoelectric artificial hand, which is operated by muscular control signals. Although, work on using neural networks for this is being carried out, this approach is not very promising due to the long learning period required for neural networks. A simulation is presented showing that not only is the EHW performance slightly better than with neural networks, but that the learning time is considerably reduced.

A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI

An array-type computer processor stops, with a plurality of computer programs held, a state control unit and a data-path unit, upon input of event data for task switching. The array-type computer processor obtains the operation state of the state control unit and the processed data of the data-path unit when stopped, and temporarily holds them for each of a plurality of the computer programs. Upon completion of this, the array-type computer processor reads the operation state and processed data of any other computer program and sets them in the state control unit and data-path unit. Upon completion of this, the array-type computer processor outputs to the state control unit the event data for starting the operation. The state control unit then starts to sequentially transfer the operation state, thereby making it possible to perform the process operations according to a plurality of computer programs in a time-sharing manner.

Array-type computer processor

In data path means, processor elements individually execute data processing in accordance with command codes described in a computer program, and switching elements individually control a connection relationship to switch among a plurality of processor elements in accordance with the command codes When an access to an external memory is made from the data path means, slave memory means generates event data indicative of a task change while temporarily holding access information for executing the access with a delay, and executes the access in place of the data path means Task changing means changes a task to be executed by the data path means when event data indicative of a task change is generated by the slave memory means

Array type processor and data processing system

This paper describes a data compression chip for the high-precision electrophotographic printer using Evolvable Hardware (EHW). EHW is a new hardware paradigm which combines Genetic Algorithm (GA) and reconfigurable hardware technology such as FPGA (Field Programmable Gate Array). In EHW, GA is used to search for the most desirable hardware structure to a given task. If the task requirement changes, GA is invoked to get a better hardware structure and EHW is reconfigured that way. In data compression, EHW is used to implement the most adequate compression method directly in hardware according to the characteristics of the target image. The EHW-based compression chip attains approximately twice the compression compared with the international standard called JBIG. This chip is the first EHW-chip to lead to a commercial product.

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Evolvable hardware chip for high precision printer image compression

Virtual hardware is difficult to implement even on recent dynamically reconfigurable processors when the loop body of the target application cannot be stored in the set of quickly switch-able contexts Here, techniques for such tough cases are proposed Differential configuration which changes only different parts of similar contexts can drastically reduce the time for re-configuration Pairwise context assignment policy can hide the overhead of configuration with double buffering Out-of-order context switching enables execution of available context in advance Through an implementation example on NEC's DRP-1, it appears that the virtual hardware can be executed with practical speed by combining the proposed techniques

Takeshi Inuo

Papers

A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI

Array-type computer processor

Array type processor and data processing system

Evolvable hardware chip for high precision printer image compression

Techniques for virtual hardware on a dynamically reconfigurable processor: An Approach to tough cases