The performance of maze-routing algorithms mapped onto linear systolic array hardware is examined. Cell expansions in the wavefront-expansion phase of maze routing are performed in parallel in each processing stage of the hardware as the routing grid streams through the processor array. The authors concentrate on optimizing the performance of single-net routing problems with respect to a given systolic hardware configuration. A heuristic called constant-increment framing is introduced as a simple method for scheduling all the required wavefront expansion steps on a pipeline of processors. One-layer and two-layer routers using this heuristic have been implemented on a prototype systolic processor. Experimental and theoretical comparisons suggest that the constant-increment heuristic exhibits performance within a factor of two of optimal over a range of hardware configurations, and is substantially easier to compute than the optimal solution. >

Systolic routing hardware: performance evaluation and optimization

The Lee routing algorithm is one of the earliest routing algorithms, and has been widely used and analysed for most aspects of automated wiring. The paper contains details of yet another modification to the basic algorithm that attempts to keep the average wiring density even over a large chip. Despite the large amount that has been published on the Lee algorithm, this particular adaptation has not been reported before. It is shown that the modification described can decrease the standard deviation of the channel wiring density by 25%.

Lee router modified for global routing

This paper describes a Full Over-the-Cell routing model to perform circuit connections over the transistors by using "transparent cells". The methodology provides flexibility and the resulting layout style presents interesting performance/cost ratios if compared to those produced by Standard Cell and traditional Over-the-Cell routing models. A symbolic environment is shown, where it is possible to make the routing over real cell layouts, based on a restriction matrix. Some special routing techniques are mentioned and practical results are shown.

A Full Over-the-Cell routing model

A general approach to gate array routing based on an abstract routing space model is presented. An efficient k-terminal net maze runner is described. It does not partition nets into two-terminal net routing problems, but solves the problem by simultaneously growing k search waves. It is shown that the explored routing space diminishes when compared to bidirectional routing schemes. Experimental data show a reduction of CPU time up to 55% and a decrease of total net length up to 6% compared to a bidirectional maze router. For k-terminal nets it is shown that net length decreases with increasing k. Additional routing space restriction is attained by use of variable search space restriction and by the introduction of a dynamic routing space partitioning method based on the concept of regions. This concept allows for determination of nonroutable nets or parts of nets in an efficient way. The new partitioning method may be implemented in any maze runner without increasing the complexity of the maze runner algorithm. Results show an additional decrease of CPU time up to 35%. >

General gate array routing using a k-terminal net routing algorithm with failure prediction

A new multiple terminul net muze runner is described thut is used in u generic plucement und routing system turgeted towards prefubricuted devices such us gate arrays and Seu-of-Gates gate urrays. Insteud of purtitioning un n-terminul net into several 2-terminul nets to be routed sequentially, we tuckle the routing problem by routing u1l terminals ut once. We show thut the explored routing space diminishes and thus the cpu-time is reduced by doing so. A new mechanism is introduced that partitions the routing spuce into so-culled 'unconnected regions'. The benefit of this is twofold. Firstly, it enubles us to identiD non-routable nets or non-routable purts of nets without uctuully trying to route them. Secondly, udditionul routing spuce restriction is possible. It is shown thut this failure prediction mechunism cun be implemented in uny muze runner scheme without increusing the complexity of the algorithm. Experimental results show an extru reduction of cpu-time up to 35% by using this new mechunism.

A Multiple Terminal Net Routing Algorithm using Failure Prediction

This paper describes a new method of restricting search space for maze routing, to achieve a higher routing completion ratio and shorter machine time. The router is applied iteratively, expanding the width of L-shaped search space restriction from narrow one to wider ones successively. Using this method, machine time was reduced to one-fourth and the routing completion ratio was more than 10% higher in experimental comparison with singly restricted routers of no iteration. This paper also discusses an analysis to help to decide the iteration number and L-shaped path width.

Takeyoshi Shirakawa

Papers

A Fast Maze Router with Iterative Use of Variable Search Space Restriction