The present invention thus provides a device structure and method for forming fin (210) Field Effect Transistors (FETs) from bulk semiconductor wafers (200) while providing improved wafer to wafer device uniformity. Specifically, the invention provides a height control layer (212), such as a damaged portion of the substrate (200) or a marker layer, which provides uniformity of fin height. Additionally, the invention provides provides isolation (214) between fins (210) which also provides for optimization and narrowing of fin width by selective oxidation of a portion (212) of the substrate relative to an oxidized portion (216) of the fin sidewalk. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

Fin fet devices from bulk semiconductor and method for forming

The invention provides a single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independent of crystal orientation. A dielectric mask (12) on a single-crystal substrate (154) is patterned to define isolating trenches. A protective conformal layer (28) is applied to the resultant structure. The conformal layer (28) on the floor of the trenches is removed and a second etch deepens the trench to expose the mesa walls which are removed during the release step by isotropic etching. A metal layer (44) is formed on the resultant structure providing opposed plates (156) and (158) of a capacitor. The cantilever beam (52) with the supporting end wall (152) extends the grid-like structure (150) into the protection of the deepened isolation trenches (54). A membrane can be added to the released structures to increase their weight for use in accelerometers, and polished for use as movable mirrors.

Microstructures and single mask, single-crystal process for fabrication thereof

We present actuators which tune the resonant frequency of micromechanical oscillators. Experimental results show resonant oscillations from 7.7% to 146% of the original resonant frequency. Numerical results substantiate these results. Two failure modes have been identified which limit

Capacitance Based Tunable Micromechanical Resonators

A semiconductor memory comprises a switching device and a charge-storage device disposed at the upper and lower sides, respectively, of each of semiconductor islands. The islands are formed on a semiconductor substrate that is completely isolated from the semiconductor substrate by an insulator. The switching device and charge-storage device are substantially the same width. The memory cell structure is extremely small. The cell structure is highly resistant to alpha-particles and is formed self-aligned. During manufacture, the SiO 2 island is oxidized adjacent its lower end to insulate the island from the substrate.

Process for manufacturing vertical dynamic random access memories

A microelectromechanical accelerometer (60) having submicron features is fabricated from a single crystal silicon substrate (10). The accelerometer includes a movable portion incorporating an axial beam (102) carrying laterally-extending high aspect ratio released fingers (110-117, 120-127) cantilevered above the floor of a cavity formed in the substrate during the fabrication process. The movable portion is supported by restoring springs (132, 142) having controllable flexibility to vary the resonant frequency of the structure. A multiple-beam structure provides stiffness in the movable portion for accuracy.

Microelectromechanical lateral accelerometer

A method of fabricating a semiconductor device which includes: (1) a step of forming an opening in a silicon substrate using a first silicon oxide film and a first silicon nitride film formed on the silicon substrate as masks, (2) a step of forming a second silicon oxide film and a second silicon nitride film on the side wall of the opening by the reduced pressure CVD method and anisotropic etching method, (3) a step of performing isotropic dry etching using the first and second silicon oxide films as masks, and (4) a step of performing heat treatment in an oxidizing atmosphere using the first and second silicon nitride films as masks. Thereby, uniform isotropic etching may be accomplished by use of the dry etching method.

Tamaki Tokuhiko

Papers

Method of fabricating semiconductor device